• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.3
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• pp.175-180
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• 2003

As the integrated circuit device shrinks to the deep submicron regime, the ion implantation process with high ion dose has been attracted beyond the conventional ion implantation technology. In particular, for the case of boron ion implantation with low energy and high dose, the stabilization and throughput of semiconductor chip manufacturing are decreasing because of trouble due to the machine conditions and beam turning of ion implanter system. In this paper, we focused to the improved characteristics of processing conditions of ion implantation equipment through the modified deceleration mode. Thus, our modified recipe with low energy and high ion dose can be directly apply in the semiconductor manufacturing process without any degradation of stability and throughput.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1559-1562
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• 2022

As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.47-52
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• 2006

This paper proposes a novel low-power $32bit\times32bit$ multiplier for deep submicron technologies beyond 130nm. As technology becomes small, static power due to leakage current significantly increases, and it becomes comparable to dynamic power. Recently, shutdown method based on MTCMOS is widely used to reduce both dynamic and static power. However, it suffers from severe power line noise when restoring whole large-size functional block. Therefore, the proposed multiplier mitigates this noise by shutting down and waking up sequentially along with pipeline stage. Fabricated chip measurement results in $0.35{\mu}m$ technology and gate-transition-level simulation results in 130nm and 90nm technologies show that it consumes $66{\mu}W,\;13{\mu}W,\;and\;6{\mu}W$ in idle mode, respectively, and it reduces power consumption to $0.04%\sim0.08%$ of active mode. As technology becomes small, power reduction efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not.

• ETRI Journal
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• v.35 no.3
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• pp.480-490
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• 2013

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large-scale asynchronous circuit, we design a fully clockless 32-bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13-${\mu}m$ CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 ${\mu}W$/MHz and is comparable to that of a synchronous counterpart.

• ETRI Journal
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• v.19 no.4
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• pp.402-413
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• 1997

A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.50-61
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• 2010

Nowadays, the SoC is watched by all over the world with interest. The design trend of the SoC is hardware and software co-design which includes the design of hardware structure in RTL level and the development of embedded software. Also the technology is toward deep-submicron and the observability of the SoC's internal state is not easy. Because of the above reasons, the SoC debug is very difficult and time-consuming. So we need a reliable debugger to find the bugs in the SoC and embedded software. In this paper, we developed a hardware debugger named OCD. It is based on IEEE 1140.1 JTAG standard. In order to verify the operation of OCD, it is integrated into the 32bit RISC processor - Core-A (Core-A is the unique embedded processor designed by Korea) and is tested by interconnecting with software debugger. When embedding the OCD in Core-A, there is 14.7% gate count overhead. We can modify the DCU which occupies 2% gate count in OCD to adapt with other processors as a debugger.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.12
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• pp.1458-1467
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• 1999

VLSI 공정 기술이 발달하면서 이웃한 전선 간의 간격이 점점 더 가까워 지고 있으며, 그에 따라 인접 전선 간의 혼신 문제가 심각해지고 있다. 본 논문에서는 3층 그리드 채널 배선에 적용 가능한 혼신을 최소화시키는 배선층 할당 방법을 제안한다. 이 방법은 선형 의사 불린 최적화 기법에 맞도록 고안되었으며, 적절한 변수 선택 휴리스틱과 상한값 추정 방법을 통하여 최적의 결과를 짧은 시간 안에 찾아낸다. 실험 결과를 통하여, 일반적인 0/1 정수 선형 프로그래밍 기법과 비교하여 성능과 수행시간 면에서 우수함을 보인다. Abstract Current deep-submicron VLSI technology appears to cause crosstalk problem severe since it requires adjacent wires to be placed closer and closer. In this paper, we deal with a horizontal layer assignment problem for three layer HVH channel routing to minimize coupling capacitance, a main source of crosstalk. It is formulated in a 0/1 integer linear programming problem which is then solved by a linear pseudo boolean optimization technique. Experiments show that accurate upper bound estimation technique effectively reduces crosstalk in a reasonable amount of running times.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.3
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• pp.1-10
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• 1997

We present an approach to high-level synthesis for a specific target architecture-partitioned bus architecture. In this approach, we have specific goals of minimizing data transfer length and number of buses in addition to common synthesis goals such as minimizing number of control steps and satisfying given resource constraint. Minimizing data transfer length and number of buses can be very important design goals in the era of deep submicron technology in which interconnection delay and area dominate total delay and area of the chip to be designed. in partitioned bus architecture, to get optimal solution satisfying all the goals, partitioning of operation nodes among segments and ordering of segments as well as scheduling and allocation/binding must be considered concurrently. Those additional goals may impose much more complexity on the existing high-level synthesis problem. To cope with this increased complexity and get reasonable results, we have employed two ideas in ur synthesis approach-extension of the target architecture to alleviate bus requirement for data transfer and adoption of genetic algorithm as a principal methodology for design space exploration. Experimental results show that our approach is a promising high-level synthesis mehtodology for partitioned bus architecture.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.569-572
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• 1998

The semiconductor technology for the deep submicron $regime(0.18\mu\textrm{m})$ and larger wafer $diameters(300\mu\textrm{m})$ has been increased its cost with each wafer. Hence, in order to reduce the number of characterization experiments of a new process, lithographic modeling is more important than it was. In this paper, we introduced a new method to extract Dill ABC parameters from the refractive index changes. In order to evaluate our exact method, results of experiments and calculations for several resists were compared with other methods〔1〕through the lithographic simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.12B
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• pp.1548-1555
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• 2011

In ultra-deep submicron technology, minimization of propagation delay and power consumption on buses is one of the most important design objectives in system-on-chip (SOC) design. Crosstalk between adjacent wires on the bus may create a significant portion of propagation delay. Elimination or minimization of such faults is crucial to the performance and reliability of SOC designs. Most of the previous works on bus encoding are targeted either to minimize the bus switching or minimize the crosstalk delay, but not both. This paper proposes a new bus encoding scheme which can adaptively select one of functions "invert" and "logic-convert" according the number of bus switching on an encoded 4-bit cluster. This scheme leads to minimization of both crosstalk and bus switching. In experiment result, our proposed encoding technique consumes about 25% less power over the previous, while completely eliminating the crosstalk delay.