• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.193-202
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• 2010

This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.

• Journal of Internet Computing and Services
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• v.12 no.3
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• pp.111-117
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• 2011

In this paper, the BER(Bit Error Rate) performance of a DVB-T2(Second Generation Digital Terrestrial Television Broadcasting System) in MISO(Multiple Input Single Output) transmission mode is evaluated by the computer simulation. In the DVB-T2 receiver, an IDD(Iterative Demapping and Decoder) technique is employed that exchanges extrinsic information between the demapper and the LDPC decoder. Simulation results show that the IDD-based DVB-T2 receiver in MISO transmission mode provides 2dB gain at BER of $10^{-4}$ but suffer from the frequency offsets between transmit antennas.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.1
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• pp.67-72
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• 2001

Convolutional code and turbo code are used in the forward and backward link of IMT-2000. In this research, we will be in consideration of Viterbi algorithm In this paper, we design Viterbi decoder with 3-bits soft decision and SMT for the convolutional code in the forward link and backward link of IMT-2000 system. The major parameters of 3-bits Viterbi decoder is determined by simulation to have identical performance with the 4-bit soft decision Viterbi decoder.

• Journal of Multimedia Information System
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• v.4 no.4
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• pp.179-188
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• 2017

The Internet Video Coding (IVC) standard is due to be published by Moving Picture Experts Group (MPEG) for various Internet applications such as internet broadcast streaming. IVC aims at three things fundamentally: 1) forming IVC patents under a free of charge license, 2) reaching comparable compression performance to AVC/H.264 constrained Baseline Profile (cBP), and 3) maintaining computational complexity for feasible implementation of real-time encoding and decoding. MPEG experts have worked diligently on the intellectual property rights issues for IVC, and they reported that IVC already achieved the second goal (compression performance) and even showed comparable performance to even AVC/H.264 High Profile (HP). For the complexity issue, however, there has not been thorough analysis on IVC decoder. In this paper, we analyze the IVC decoder in view of the time complexity by evaluating running time. Through the experimental results, IVC is 3.6 times and 3.1 times more complex than AVC/H.264 cBP under constrained set (CS) 1 and CS2, respectively. Compared to AVC/H.264 HP, IVC is 2.8 times and 2.9 times slower in decoding time under CS1 and CS2, respectively. The most critical tool to be improved for lightweight IVC decoder is motion compensation process containing a resolution-adaptive interpolation filtering process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.80-83
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• 2010

This paper describes an analysis of decoding performance of multi-mode LDPC(Low Density Parity Check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3,3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder which adopts min-sum algorithm and layered decoding scheme is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, bit-width of integer and fractional parts, an optimal design condition and decoding performance of LDPC decoder are analyzed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.1-8
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• 2004

Viterbi decoders are widely used for communication and high-density storage devices. An add-compare-select(ACS) unit has been an active research area for a long time because it is the most critical component in determining the operation speed and power-consumption of the Viterbi decoder. We propose a new comparator which is faster and consumes less power than existing ones. We also used the new comparator for a Viterbi decoder and our simulations results show the Viterbi decoder outperforms existing ones at least $20\%$ in its operating speed.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.72-79
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• 2014

This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.44-51
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• 2010

This paper proposes the architecture of high-performance Viterbi decoder circuit. The proposed circuit does not require additional memory to calculate the branch metrics because it uses the characteristics of the branch data. The speed of the Viterbi decoder circuit is increased up to 75% by rearranging the path metric data in SRAM and registers properly for fast add-compare-select operations. We described the proposed Viterbi decoder circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The synthesized circuit consists of 8,858 gates and its maximum operating frequency is 130MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.8
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• pp.1839-1844
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• 2015

The low-density parity-check(LDPC) code has been adopted in many communication standards due to its error correcting performance, and the quasi-cyclic LDPC(QC-LDPC) is widely used because of implementation easiness. In the QC-LDPC decoder, a cyclic-shifter is required to rotate data in various sizes. This kind of cyclic-shifters are called multi-size circular shifter(MSCS), and this paper proposes a low-complexity structure for MSCS. In the conventional serially-placed two barrel-rotators, the unnecessary multiplexers are revealed and removed, leading to low-complexity. The experimental results show that the area is reduced by about 12%.

• Journal of Communications and Networks
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• v.16 no.6
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• pp.639-644
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• 2014

In low-density parity-check (LDPC) coded multiple-input multiple-output (MIMO) communication systems, probabilistic information are exchanged between an LDPC decoder and a MIMO detector. TheMIMO detector has to calculate probabilistic values for each bit which can be very complex. In [1], the authors presented a class of linear block codes named low-density MIMO codes (LDMC) which can reduce the complexity of MIMO detector. However, this code only supports the outer-iterations between the MIMO detector and decoder, but does not support the inner-iterations inside the LDPC decoder. In this paper, a new approach to construct LDMC codes is introduced. The new LDMC codes can be encoded efficiently at the transmitter side and support both of the inner-iterations and outer-iterations at the receiver side. Furthermore they can achieve the design rates and perform very well over MIMO channels.