• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.743-750
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• 2000

In this paper, low-power block filtering architecture for digital If down sampler and up sampler is proposed. Software radio technology requires low power and cost effective digital If down and up sampler. Digital If down sampler and up sampler are accompanied with decimation filter and interpolation filter, respectively. In the proposed down sampler architecture, it is shown that the parallel and low-speed processing architecture can be produced by cancellation of inherent up sampler of block filter and down sampler. Proposed up sampler also utilizes cancellation of up sampler and inherent down sampler of block filtering structure. The proposed architecture is compared with the conventional polyphase architecture.

• Journal of the Korea Society of Computer and Information
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• v.17 no.2
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• pp.113-118
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• 2012

In this paper, we discuss the design of the Digital Down Converters for the IEEE 802.11 wireless LAN receiver, which can be used for the customized receiver. The customized receiver can be used for special puropsed services which cannot be realized using the general custom chip. In the OFDM receiver, DDC receives the up sampled Inphase/Quadrature signal from the AD converter and process down sampling and filtering procedures using the Cascaded Intergrator Filter and FIR filters. We discuss the structure and design methodology of DDC's and analyze the simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.8A
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• pp.671-678
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• 2005

This paper proposed symbol rate method which does not require a priori knowledge on the symbol rate and simplified modulation identification method to classify BPSK, QPSK, 8PSK signal. In order to estimate the unknown symbol rate, sliding FFT and simple moving average to estimate the spectrum of the signals is utilized, and sliding window and decimation, LPF blcok to estimate the proper symbol rate is used. Although conventional modulation ID method must use SNR value as the test statistics, the receiver cannot estimate the SNR value since the receiver cannot know the modulation type at the start of communication, and bit resolution is high due to using nonlinear function such as log, cosh. Therefore, we proposed the simplified fixed SNR value method. The performance of symbol rate estimation and modulation ID is shown using Monte Carlo computer simulation. This paper show that symbol rate estimation also has good performance in low SNR, and proposed simplified fixed SNR method has almost equivalent performance compared to conventional method.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.3
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• pp.165-169
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• 2008

Analog-to-Digital converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental converters provide a solution for such measurement applications, as they retain most of the advantages of conventional ${\Delta}{\Sigma}$ converters, and yet they are capable of offset-free and accurate conversion. Most of the previous research on incremental converters was for single-channel and dc signal applications, where they can perform extremely accurate data conversion with more than 20-bit resolution. In this paper, a design technique for implementing multiplexed incremental data converters to convert narrow bandwidth ac signals is discussed. A design methodology to optimize the signal-to-quantization+thermal noise ratio of multiplexed IDC is presented. It incorporates the operation principle, topology, and digital decimation filter design. The theoretical results are verified by simulation results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.2
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• pp.309-314
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• 2008

Analog-to-digital converters(ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental(integrating) data converters(IDCs) provide a solution for such measurement applications, as they retain most of the advantages of conventional $\Delta{\Sigma}$ converters, and yet they are capable of offset-free and accurate conversion. In this paper, a design technique for implementing multiplexed incremental data converters to convert narrow bandwidth AC signals over multi-channel is discussed. It incorporates the operation principle, topology, and digital decimation filter design. The theoretical results are verified by simulation results.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.47-50
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• 2002

An extended-counting analog to digital converter (ADC) is designed to have a high resolution(14bit) with low power consumption and small dia area. First order sigma-delta modulator with a simple counter for incremental operation eliminates the need of big decimation filter in conventional sigma-delta type ADC. To improve the accuracy and linearity, extended mode of successive approximation is followed. For 14-bit conversion operation, total 263 clocks(1 clock for reset, 256 clocks for incremental operation and extended 6 clocks for successive approximation operation) are needed with the sampling rate of 10 Ms/s This ADC is implemented in a 0.6um standard CMOS technology with a die area of 1 mm ${\times}$ 0.75 mm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.8B
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• pp.1092-1099
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• 2001

본 논문에서는 무선 통신 시스템의 중간주파수 처리 단을 디지털로 신호 처리하는 DDC(Digital Down Converter)의 저전력 아키텍처를 제안한다. FIR 필터의 계산량을 줄이기 위해서 개발된 Interpolated FIR 필터가 DDC의 데시메이션 필터로 널리 사용되고 있다. 본 논문은 이와 같은 Interpolated FIR 필터의 개념이 IIR 필터에도 적용될 수 있음을 보이고, 전력 소모와 구현 면적이 기존의 Interpolated FIR 구조보다 더욱 감소된 Interpolated IIR 필터 구조를 제안하였다. CDMA IS-95 DDC 사양의 데시메이션 필터를 FIR 구조, Interpolated FIR 구조, IIR 구조, Interpolated IIR 구조로 구현하여 이 4가지 구조들의 전력소모와 구현 면적을 비교하였으며 제안된 Interpolated IIR 구조가 기존의 Interpolated FIR 구조에 비하여 15.2%의 소모전력 감소와 35.3%의 구현면적의 감소를 달성할 수 있음을 보인다.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.1
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• pp.33-36
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• 2009

Incremental converters provide a solution for such measurement applications, as they retain most of the advantages of conventional ${\Delta}{\Sigma}$ converters, and yet they are capable of offset-free and accurate conversion. Most of the previous research on incremental converters was for single-channel and dc signal applications, where they can perform extremely accurate data conversion with more than 20-bit resolution. In this paper, a design technique for implementing multi-channel incremental data converters to convert narrow bandwidth ac signals is discussed. It incorporates the operation principle, topology, and digital decimation filter design. The theoretical results are verified by simulation results.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.110.1-110.1
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• 2016

국내외 최첨단 반도체 및 평판 디스플레이 공정에서 필요한 개별 건식 진공펌프들의 자기진단을 통한 예지보수의 실시간 구현 장치 개발과제의 2차년 전반기 수행된 연구결과의 일부를 본 논문에서 소개한다. 본 연구에서 최종 목표로 설정하고 있는 "smart" 진공펌프란 운전상태에 관련된 변수들의 측정치를 기반으로 한 자기진단 (self-diagnostics) 기능을 내장한 차세대 공정용 진공펌프를 의미한다. 1차년에 선정된 상태진단용 진공펌프의 상태변수(state variable)들의 효과적인 수집을 구현하기 위한 연구가 진행되었다. 기존의 반도체 공정용 진공펌프들에서 측정하고 있는 상태변수로는 온도, 유량, 배기관 압력, 모터 소비전류 등과 같은 정적인 변수들뿐 아니라, 회전기계류의 상태진단에 필수적인 진동신호를 추가한 상태 변수 수집 장치를 개발하였다. 본 연구팀은 진공펌프의 회전진동을 유발하는 대표적인 부품은 회전체, 베어링, 그리고 치차로 이들 3 종의 회전진동성분들을 효과적으로 측정할 수 있는 신호처리 기법을 개발하였다. 금번 연구에서 채택한 진동신호 처리기법은 초고속 FFT 변환 기반의 주파수 대역 별 진동 레벨 환산과 더불어 다단계로 구성된 디지털 필터 (multi-staged decimation filter) 기법을 개발 적용하였다. 이러한 신호처리 기법을 통하여 측정된 진동 신호로부터 회전체, 베어링, 그리고 치차의 회전 진동성분을 효과적으로 측정하는 방법을 금번 학술대회에서 소개한다. 그리고, 진공펌프 상태진단에 필요한 상태변수의 실시간 backup 방법, 그리고 공정관리 server와 통신기능, 그리고 펌프 현장 관리자용 PC와 통신 기법 등 상태변수 측정 모듈의 확장성에 대한 기술적 내용을 소개한다.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.4
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• pp.167-174
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• 2002

This study describes a fetal heart rate(FHR) estimation algorithm using phonogram. Using a phonogram amplifier, various fetal heart sounds are collected in a university hospital. The FHR estimation algorithms consists of a lowpass filter, decimation, envelop detection, pitch detection, and post-processing. The post-processing is the FHR decision procedure using all informations of fetal heart rates. Using the algorithm and other parameters of fetal heart sound, a fetal monitoring software was developed. This can display the original signals, the FFT spectra, FHR and its trajectory. Even though the fetal phonogram amplifier detects the fetal heart sounds well, the sound quality is not so good as the ultrasonography. In case of very week fetal heart sound, autocorrelation of it showed clear periodicity. But two main peaks in one period is an obstacle in pitch detection and peaks are not so vivid. The proposed FHR estimation algorithm showed very accurate and stable results. Since the developed software displays multiple parameters in real time and has convenient functions, it will be useful for the phonogram-style fetal monitoring device.