• 대한전자공학회논문지SD
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• 제46권12호
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• pp.58-65
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• 2009

본 논문에서는 캐패시터로 상승 시간과 하강 시간을 조절하고 슈미트 트리거의 스위칭 전압을 이용한 데드 타임 회로를 갖는 고전압 구동 IC (High Voltage Gate Driver IC)를 설계하였다. 설계된 고전압 구동 IC는 기존 회로와 비교하여 온도에 따 른 데드 타임 변동을 약 52% 줄여 하프브리지 컨버터의 효율을 증대시켰으며 캐패시터 값에 따라 가변적인 데드 타임을 가진다. 또한 숏-펄스 (short-pulse) 생성회로를 추가하여 상단 레벨 쉬프트 (High side part Level shifter)에서 발생하는 전력소모를 기존의 회로에 비해 52% 감소 시켰고, UVLO를 추가하여 시스템의 오동작을 방지하여 시스템의 안정도를 향상시켰다. 제안한 회로를 검증하기 위해 Cadence의 Spectre을 이용하여 시뮬레이션 하였고 1.0um 공정을 이용하였다.

• 전기전자학회논문지
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• 제16권3호
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• pp.203-210
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• 2012

기존의 DC-DC 부스트 변환기에 사용되는 non-overlapping gate driver는 dead-time이 고정되어 있기 때문에 body-diode conduction loss 또는 charge-sharing loss가 발생하는 문제점을 가지고 있다. 이러한 loss에 의한 효율 감소를 줄이기 위해 본 논문에서는 dead-time 적응제어 기능을 갖는 PWM DC-DC 부스트 변환기를 설계하였다. 제안된 DC-DC 부스트 변환기는 CMOS $0.35{\mu}m$ 공정으로 설계되었고, 입력전압 2.5V를 받아서 3.3V의 출력전압으로 승압시킨다. 스위칭 주파수는 500kHz이며, 최대효율은 97.3%이다.

• 한국전기전자재료학회논문지
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• 제22권10호
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• pp.801-807
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• 2009

In this paper, we propose a novel shoot-through protection circuit and pulse generator for half-bridge driver IC. We designed a robust half-bridge driver IC over a variation of processes and power supplies. The proposed circuit is composed a delay circuit using a beta-multiplier reference. The proposed circuit has a lower variation rate of dead time and pulse-width over variation of processes and supply voltages than the conventional circuit. Especially, the proposed circuit has more excellent pulse-width matching of set and reset signals than the conventional circuit. Also, the proposed pulse generator is prevented from fault operations using a logic gate. Dead time and pulse-width of the proposed circuit are typical 250 ns, respectively. The variation ratio is 68%(170 ns) of maximum over variation of processes and supply voltages. The proposed circuit is designed using $1\;{\mu}m$ 650 V BCD (Bipolar, CMOS, DMOS) process parameter, and the simulations are carried out using Spectre simulator of Cadence corporation.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 추계학술대회
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• pp.285-288
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• 2012

기존의 DC-DC Boost 변환기에 사용되는 일반적인 non-overlapping gate driver는 dead-time이 고정되어 있기 때문에 body-diode conduction loss 또는 charge-sharing loss가 발생하는 문제점이 있다. 따라서 본 논문에서는 이러한 loss에 의한 효율 감소를 줄이기 위해 dead-time 적응제어 기능을 갖는 PWM DC-DC Boost 변환기를 설계하였다. 또한, 부하전류가 작은 경우 효율을 증가시키기 위해 power switching 회로를 사용하였다. 그 결과 넓은 부하 전류 범위에서 높은 효율을 얻을 수 있다. 제안된 DC-DC Boost 변환기는 CMOS 0.18um공정으로 설계하였다. 2.5V의 입력전압을 받아서 3.3V의 출력전압을 얻는다. 스위칭 주파수는 500kHz이며, 최대효율은 97.8%이다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.361-364
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• 2013

기존의 DC-DC 부스트 변환기에서 사용되는 non-overlapping gate driver는 dead-time이 고정되어 있기 때문에 body-diode conduction loss 또는 charge-sharing loss가 발생하는 문제점을 가지고 있다. 이러한 손실을 줄이기 위해 사용된 기존의 적응제어 방식의 경우는 CCM 동작 시 전력트랜지스터가 동시에 on이 되는 구간이 발생하여 시스템 효율이 감소하는 문제점이 있다. 따라서 본 논문 에서는 이러한 문제점을 해결할 dead-time 적응제어 기능과 power switching 기능을 갖는 DC-DC 부스트 변환기를 설계 하였다. CMOS 0.35um 공정을 사용하였고, 2.5V 입력으로 3.3V의 출력전압을 얻으며, 스위칭 주파수는 500kHz 이다. 부하전류 150mA일 때 가장 높은 95.3%의 효율을 얻었다. 설계된 회로의 칩 면적은 $1720um{\times}1280um$이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.11-12
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• 2009

In this paper, we propose a high voltage driver IC(HVIC) for LCD and PDP TV power supply. The proposed circuit is included novel a shoot-through protection and a pulse generation circuit for the high voltage driver IC. The proposed circuit has lower variation of dead time and pulse-width about a variation of a process and a supply voltage than a conventional circuit. Especially, the proposed circuit has more excellent pulse-width matching of set and reset signals than the conventional circuit. Also the proposed pulse generation circuit prevent from fault operations using a logic gate. Dead time and pulse-width of the proposed circuit are typical 250 ns, and its variation is maximum 170 ns(68 %) about a variation of a process and a supply voltage. The proposed circuit is designed using $1\;{\mu}m$ 650 V BCD process parameter, and a simulation is carried out using Spectre.

• Journal of Power Electronics
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• 제15권4호
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• pp.861-875
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• 2015

This paper presents a wide frequency range LLC resonant controller IC for LED backlight units. In this paper a new phase-domain resonance deviation prevention circuit (RDPC), which covers a wide frequency and input voltage range, is proposed. In addition, a wide range gate clock generator and an automatic dead time generator are proposed. The chip is fabricated using 0.35 μm BCD technology. The die size is 2 x 2 mm2. The frequency of the clock generator ranges from 38 kHz to 400 kHz, and the dead time ranges from 300 ns to 2 μs. The current consumption of the LLC resonant controller IC is 4 mA for a 100 kHz operation frequency using a supply voltage of 15 V.

• Journal of Power Electronics
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• 제12권6호
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• pp.886-894
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• 2012

This paper presents a secondary-side, dual-mode feedback LLC resonant controller IC with dynamic PWM dimming for LED backlight units. In order to reduce the cost, master and slave outputs can be generated simultaneously with a single LLC resonant core based on dual-mode feedback topologies. Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) schemes are used for the master stage and slave stage, respectively. In order to guarantee the correct dual feedback operation, Phased-Locked Loop (PLL)-based automatic duty control circuit is proposed in this paper. The chip is fabricated using $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology, and the die size is $2.5mm{\times}2.5mm$. The frequency of the gate driver (GDA/GDB) in the clock generator ranges from 50 to 425 kHz. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply. The duty ratio of the slave stage can be controlled from 40% to 60% independent of the frequency of the master stage.

• Journal of Power Electronics
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• 제11권3호
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• pp.271-278
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• 2011

This paper presents a LLC resonant controller IC for secondary side control without external active devices to achieve low profile and low cost LED back light units. A gate driving transformer is adopted to isolate the primary side and the secondary side instead of an opto-coupler. A new integrated dimming circuitry is proposed to improve the dynamic current control characteristic and the current density of a LED for the brightness modulation of a large screen LCD. A dual-slope clock generator is proposed to overcome the frequency error due to the under shoot in conventional approaches. This chip is fabricated using 0.35 ${\mu}m$ BCD technology and the die size is $2{\times}2\;mm^2$. The frequency range of the clock generator is from 50 kHz to 500 kHz and the range of the dead time is from 50 ns to 2.2 ${\mu}s$. The efficiency of the LED driving circuit is 97 % and the current consumption is 40 mA for a 100 kHz operation frequency from a 15 V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.109-116
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• 2014

This paper presents a high-efficiency digital class-D audio amplifier using a composite interpolation filter for portable audio devices. The proposed audio amplifier is composed of an interpolation filter, a delta-sigma modulator, and a class-D output stage. To reduce power consumption, the designed interpolation filter has an optimized composite structure that uses a direct-form symmetric and Lagrange FIR filters. Compared to the filters with homogeneous structures, the hardware cost and complexity are reduced by about half by the optimization. The coefficients of the digital delta-sigma modulator are also optimized for low power consumption. The class-D output stage has gate driver circuits to reduce shoot-through current. The implemented class-D audio amplifier exhibited a high efficiency of 87.8 % with an output power of 57 mW at a load impedance of $16{\Omega}$ and a power supply voltage of 1.8 V. An outstanding signal-to-noise ratio of 90 dB and a total harmonic distortion plus noise of 0.03 % are achieved for a single-tone input signal with a frequency of 1 kHz.