• International Journal of Control, Automation, and Systems
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• v.5 no.1
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• pp.79-85
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• 2007

In this paper, a real-coded genetic algorithm is proposed for identification of time delay systems from step responses. FOPDT(First-Order Plus Dead-Time) and SOPDT(Second-Order Plus Dead-Time) systems, which are the most useful processes in this field, but are difficult for system identification because of a long dead-time problem and a model mismatch problem. Genetic algorithms have been successfully applied to a variety of complex optimization problems where other techniques have often failed. Thus, the modified crossover operator of a real-code genetic algorithm is proposed to effectively search the system parameters. The proposed method, using a real-coding genetic algorithm, shows better performance characteristics when compared to the usual area-based identification method and the directed identification method that uses step responses.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.58-65
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• 2009

In this paper, we designed high voltage gate drive IC including dead time circuit in which capacitors controlled rising time and falling time, and schimitt-triggers controlled switching voltage. Designed High voltage gate drive IC improves an efficiency of half-bridge converter by decreasing dead time variation against temperature and has variable dead time by the capacitor value. and its power dissipation, which is generated on high side part level shifter, has decreased 52 percent by short pulse generation circuit, and UVLO circuit is designed to prevent false-operation. We simulated by using Spectre of Cadence to verify the proposed circuit and fabricated in a 1.0um process.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1645-1650
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• 2005

FOPDT(First-Order Plus Dead-Time) and SOPDT(Second-Order Plus Dead-Time) process, which are used as the most useful process in industry, are difficult about process identification because of the long dead-time problem and the model mismatch problem. Thus, the accuracy of process identification is the most important problem in FOPDT and SOPDT process control. In this paper, we proposed the real-coded genetic algorithm for identification of FOPDT and SOPDT processes. The proposed method using real-coding genetic algorithm shows better performance characteristic comparing with the existing an area-based identification method and a directed identification method that use step-test responses. The proposed strategy obtained useful result through a number of simulation examples.

• 전기의세계
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• v.18 no.1
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• pp.15-23
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• 1969

A lot of recent researches have shown that a Pseudo Random Binary Signal is a quite effective test signal to measure the impulse response of a plant. Generally speaking, however, such a response itself is not satisfactory to determine the appropriate control parameters or control inputs. Here, the author intends to estimate the unknown parameters of the First Order Plant with Dead Time by means of correlation method using M-sequence signal. The time constant T and the dead time L of the plant are eatimated with one tracking loop by automatically adjusting delay time .tau. of M-sequence signal according to variations of T and L. In this paper, a three level M-sequence signal is used as a test signal in order to avoid troublesome operations to calculate partial derivatives of a given performance index with respect to the parameters which are usually required in the Model Method. Several experiments with analogue computer using low pass filters as averaging circuits showed good results as expected.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.59-60
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• 2015

본 논문에서는 3-Level NPC(Neutral Point Clamped) 인버터에서 ZDPWM(Zero Dead Time Pulse Width Modulation) 기법에 대해서 제안한다. 3-Level NPC 인버터에서 기존 PWM 기법은 각 스위치는 서로 상보적인 동작을 수행하고, 반도체 스위칭 소자 특성상 Rise Time과 Fall Time의 시간차이로 인하여 단락사고를 방지하기 위해 스위칭 신호의 Rising Edge에 데드타임을 인가하여 단락을 방지한다. 그러나 이러한 데드타임은 지령 스위칭 신호와 실제 스위칭 신호의 오차로 인하여 출력 전압 및 전류에 왜곡이 발생하고, 이러한 왜곡으로 인하여 시스템의 오작동 및 직류링크단 전압의 불평형의 원인이 된다. 제안하는 PWM기법은 지령전압과 출력전류의 위상에 따라 영역을 나눈 후 전류의 방향에 따라 옵셋 전압을 생성하여 새로운 지령전압을 만들어 각 스위치에 스위칭 신호를 인가한다. 제안한 기법에 타당성을 증명하기 위해 시뮬레이션을 통해 검증하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.361-364
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• 2013

Since the non-overlapping gate driver used in conventional DC-DC boost converters generates fixed dead-times, the converters suffer from the body-diode conduction loss or the charge-sharing loss. A adaptive control method has been proposed to reduce these loses. In this method, however, occurrence of and overlapping time of two power transistors in CCM results in reduction of efficiency. In this paper, to overcome this problem a new adaptive control method in proposed, and a DC-DC boost converter with the proposed adaptive control and power switching has been designed in a 0.35um CMOS process. The designed converter outputs 3.3V from a input voltage of 2.5V. The switching frequency is 500kHz and the maximum power efficiency is 95.3% at a load current 150mA. The designed chip area is $1720um{\times}1280um$.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.111-117
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• 1998

This paper presents a polarity changing method without dead time of a cycloconverter with an LC resonant circuit. According to the proposed method, dead time to prevent short circuit for the polarity changing is not required. Therefore the delay of control and the harmonic components of output currents can be decreased. And the proposed method can be expanded for the other natural commutated cycloconverters of noncirculating current type. In this paper, the switching method of the proposed polarity changing without dead time is studied, and in order to confirm the validity of the proposed method the experiment is carried out with a cycloconverter with an LC resonant circuit.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.3
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• pp.201-208
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• 2015

The effects of dead-time and offset error, which cause output current distortion in single-phase grid-connected inverters are investigated this paper. Offset error is typically generated by measuring phase current, including the voltage unbalance of analog devices and non-ideal characteristics in current measurement paths. Dead-time inevitably occurs during generation of the gate signal for controlling power semiconductor switches. Hence, the performance of the grid-connected inverter is significantly degraded because of the current ripples. The current and voltage, including ripple components on the synchronous reference frame and stationary reference frame, are analyzed in detail. An algorithm, which has the proportional resonant controller, is also proposed to reduce current ripple components in the synchronous PI current regulator. As a result, computational complexity of the proposed algorithm is greatly simplified, and the magnitude of the current ripples is significantly decreased. The simulation and experimental results are presented to verify the usefulness of the proposed current ripple reduction algorithm.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.2B no.3
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• pp.81-89
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• 2002

The sensorless AC motor drive is a popular topic of study due to the cost and reliability of speed and position sensors. Most sensorless algorithms are based on the mathematical modeling of motors including electrical variables such as phase current and voltage. Therefore, the accuracy of such variables largely affects the performance of the sensorless AC motor drive. However, the output voltage of the SVPWM-VSI, which is widely used in sensorless AC motor drives, has considerable errors. In particular, the SVPWM-VSI is error-prone in the low speed range because the constant DC link voltage causes poor resolution in a low output voltage command and the output voltage is distorted due to dead time and voltage drop. This paper investigates a novel high-performance strategy for overcoming these problems in a sensorless ac motor drive. In this paper, a variation of the DC link voltage and a direct compensation for dead time and voltage drop are proposed. The variable DC link voltage leads to an improved resolution of the inverter output voltage, especially in the motor's low speed range. The direct compensation for dead time and voltage drop directly calculates the duration of the switching voltage vector without the modification of the reference voltage and needs no additional circuits. In addition, the proposed strategy reduces a current ripple, which deteriorates the accuracy of a monitored current and causes torque ripple and additional loss. Simulation and experimentation have been performed to verify the proposed strategy.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.5
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• pp.269-277
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• 1999

In this paper, a novel dead time minimization algorithm is proposed for improving the output waveform of an inverter. The adverse effects of the dead time are mainly described by the voltage drop and the distortion factor of waveforms. The principle of the proposed algorithm is organized with forbidding unnecessary firings fo the inverter switches which are not conducted even though the gate signal is impressed. The proposed methods are explained with the conduction mode of output currents. The H/W and S/W implementation method of the proposed algorithm are also presented. The validity of the proposed algorithm is verified by comparing the simulation and experimental results with conventional methods. It can be concluded from the results that the proposed algorithm has the advantage which is able to reduce the harmonics in the output voltages and which the output voltage can nearly be equal to the reference value. Another advantage of the proposed method is the reduction of total numbers of switching so that the switching losses of inverter drives can be minimized.