• Proceedings of the Polymer Society of Korea Conference
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• 2006.10a
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• pp.27-28
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• 2006

Chromatographic separation of enantiomers by high-performance liquidchromatography (HPLC) has considerably advanced in the past two, and many optically active polymers have been developed to be usedaschiral stationary phases (CSP). Among many CSPs, cellulose-andamylose-based CSPs are most attractive from the viewpoints of theirwide applicability and easy availability. The polysaccharides are readily modified to ester and carbamates. The derivatives have been used as CSPs after being coated on macroporus silica gel. Here, the CSPs based on phenylcarbamate derivatives of these two polysaccharides will be mainly discussed. The immobilization of the derivatives on silica gel will also be discussed.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.883-886
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• 1998

We introduce a high level synthesis methodlogoy for automatic synthesis of asynchronous circuits form a language based on CSP. The input language is a high level concurrent algorithmic specification that can model complex concurrent control flow, logical and arithmetic computation and communications between them. This specification is translated into petri net which has actions. These actions are refined to synthesize the controllers and to allocate the data resources. We use the automatic synthesis through signal transition graphs (STGs) that allows to take advantage of logic synthsis methods to optimize the circuit.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.12a
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• pp.45-61
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• 1999

General trend in electronics industry towards multimedia in the 21 century is presented here. All equipments require fast graphic processing together with thin and lightweight assembly technology. In Japan, CSP was developed and applied to mobile equipments for several years, and recently stacked die assembly technology is being developed. In addition, so-called flip chip technology is also being developed and which is applied to MCP and MCM little by little these days. Here current packaging technology in Japan is presented including above.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.12a
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• pp.155-162
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• 1999

A bare chip packaging technology by an encapsulated flip chip bonding on a build-up printed circuit board has emerged in 1991. Since then, it enabled a high density and low cost semiconductor packaging such as a direct chip bonding on mother board and high density surface mount components, such as BGA and CSP. This technology can respond to various requirements from applications and is considered to take over a main role of semiconductor packaging in the next decade.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.12a
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• pp.127-154
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• 1999

Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

• Journal of Applied Reliability
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• v.2 no.2
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• pp.85-97
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• 2002

In this paper, partially repairable concurrent spare parts requirement determination problem of newly procured equipment systems is considered. “partially repairable” means that a portion of damaged parts can be recover their function and reused after repairs. A mathematical model is derived for making an CSP requirement determination subject to the constraint of satisfying any given operational availability limitation. We assume that the failure of a part follows a Poisson process and the repair time has an exponential distribution. Using the generalized Lagrange multipliers method, the solution procedure is derived.

• Journal of the Korean Operations Research and Management Science Society
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• v.17 no.3
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• pp.159-170
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• 1992

The size of time constaints is the critical bottleneck of the Crew Scheduling Problem (CSP). This paper deals with a method to extract the minimum required time constraints by k-shortest path algorithm. These time constraints are added as the "insurance constraints" to avoid the unnecessary tree search, which are very time-consuming procedures, for the integer solutions. The computational results show that the problem size in LP formulation could be reduced by our method.

• Proceedings of the Microbiological Society of Korea Conference
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• 2002.10a
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• pp.151-158
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• 2002

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04b
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• pp.1237-1240
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• 2001

최근 제품의 초소화와 반도체의 고집적화로, 작은 크기로 많은 리드를 제공하기 위해, 부품 밑면에 격자형태로 볼이 배열되어 있는 BGA나 CSP부품들이 최근 많이 이용되고 있다. 하지만, BGA는 한번 PCB에 장착되면, 볼 외관검사가 원천적으로 불가능하므로, 부품을 장착하기 전에 볼 품질의 검사와 부품의 정밀한 위치 및 각도의 측정이 요구된다. 본 논문에서는 BGA부품의 위치 및 각도를 추출하기 위한 방법과 볼을 검사하기 위한 알고리즘을 소개한다.

• Journal of the Korean Operations Research and Management Science Society
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• v.11 no.2
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• pp.69-78
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• 1986

The outlook for the Civil Service Pension (CSP) program in Korea indicates several problems. First, the balance of the benefit among the pension recipients is not well maintained. Second, the program is running out of funds as benefit increases exceed the growth in revenues. In this article, we analyze these problems by using linear programming model and discuss the alternatives. We propose an addition of the age limit to the benefit eligibility and a reconsideration of the government subsidy's level.