• 한국재료학회지
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• 제9권2호
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• pp.124-131
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• 1999

Copper film, which is expected to be used as interconnection material for 1 giga DRAM integrated circuits was deposited on hole and trench patterns by Metal Organic Chemical Vapor Deposition(MOCVD) method. After a reflow process, contact and L/S patterns were filled by copper and the characteristics of the Cu reflow process were investigated. When deposited Cu films were reflowed, grain growth and agglomeration of Cu have occurred in surfaces and inner parts of patterns as well as complete filling in patterns. Also Cu thin oxide layers were formed on the surface of Cu films reflowed in $O_2$ambient. Agglomeration and oxidation of Cu had bad influence on the electrical properties of Cu films especially, therefore, their removal and prevention were studied simultaneously. As a pattern size is decreased, preferential reflow takes place inside the patterns and this makes advantages in filling patterns of deep submicron size completely. With Cu reflow process, we could fill the patterns with the size of deep sub-micron and it is expected that Cu reflow process could meet the conditions of excellent interconnection for 1 giga DRAM device when it is combined with Cu MOCVD and CMP process.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.82-82
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• 2007

The chemical mechanical polishing (CMP) process has been widely used to obtain global planarization of multilevel interconnection process for ultra large scale. integrated circuit applications. Especially, the application of copper CMP has become an integral part of several semiconductor device and materials manufacturers. However, the low-k materials at 65nm and below device structures because of fragile property, requires low down-pressure mechanical polishing for maintaining the structural integrity of under layer during their fabrication. In this paper, we studied electrochemical mechanical polishing (ECMP) as a new planarization technology that uses electrolyte chemistry instead of abrasive slurry for copper CMP process. The current-voltage (I-V) curves were employed we investigated that how this chemical affect the process of voltage induced material removal in ECMP of Copper. This work was supported by grant No. (R01-2006-000-11275-0) from the Basic Research Program of the Korea Science.

• Korean Chemical Engineering Research
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• 제47권2호
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• pp.141-149
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• 2009

초고속 연산용 CMOS(complementary Metal Oxide Semiconductor) 배선재료로 사용되고 있는 구리(Cu)가, 기가급 메모리 소자용 금속 배선 물질에도 사용이 시작되면서 구리 박막에 대한 재료 및 공정이 새로운 조명을 받고 있다. 반도체 금속 배선에 사용하는 수 nm 두께의 구리 박막의 형성에 전해도금(electrodeposition)과 무전해 도금(electroless deposition) 같은 전기화학적 방법을 이용하게 되어서 표면 처리, 전해액 조성과 같은 중요한 요소에 대한 최신 연구 동향을 요약하였다. 구리 박막에서 구리 배선을 제작하여야 하므로 새로운 패턴 기술인 상감기법이 도입되어, 구리도금과 상감기법과의 공정 일치성 관점에서 전해도금과 무전해 도금의 요소 기술에 대해 기술하였다. 구리보다 비저항이 낮아 차세대 소자용 배선에 있어서 적용이 예상되는 은(Ag)을 전기화학적 방법으로 금속 배선에 적용하는 최신 연구에 대하여도 소개하였다.

• 마이크로전자및패키징학회지
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• 제22권4호
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• pp.37-46
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• 2015

본 논문에서는 PCB용 카본 CCL의 열전달 특성을 실험과 수치해석을 통해 연구하였는데 카본 CCL의 특성 연구를 위해 기존 FR-4 코어와 Heavy copper 코어를 적용한 PCB를 비교하였다. 열전달특성 분석을 위해 코어는 한 개와 두 개가 적용된 HDI PCB 샘플이 제작되었고, 카본코어는 Pan grade와 pitch grade의 2종이 적용되었으며, 코어 두께에 의한 열전달 특성도 평가되었다. 연구결과에 의하면 카본 코어의 열전달 특성은 heavy copper 코어보다는 낮으나 FR-4 코어보다는 우수하였다. 또한, 카본 코어와 heavy copper 코어는 두께가 증가할수록 열전달 특성이 높아졌으나 FR-4 코어는 두께가 증가할수록 열전달 특성이 낮아졌다. heavy copper 코어 적용시 드릴마모도 증가, 무게 증가, 전기절연성 확보를 위한 절연재의 추가로 원가상승을 고려할 때 카본 코어가 PCB의 열전달 특성 향상을 위한 대안이 될 것으로 판단된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.537-537
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• 2008

Copper (Cu) has been widely used for interconnection structure in intergrated circuits because of its properties such as a low resistance and high resistance to electromigration compared with aluminuim. Damascene processing for the interconnection structure utilizes 2-steps chemical mechanical polishing(CMP). After polishing, the removal of abrasive particles on the surfaces becomes as important as the polishing process. In the paper, buffing process for the removal of colloidal silica from polished Cu wafer was proposed and demonstrated.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.188-188
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Meta Oxide Semiconductor) based electronic devices, the electronic devices, become much faster and smaller size that are promising property of semiconductor market. However, very narrow interconnect line width has some disadvantages. Deposition of conformal and thin barrier is not easy. And metallization process needs deposition of diffusion barrier and glue layer for EP/ELP deposition. Thus, there is not enough space for copper filling process. In order to get over these negative effects, simple process of copper metallization is important. In this study, Cu-V alloy layer was deposited using of DC/RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane SiO2/Si bi-layer substrate with smooth surface. Cu-V film's thickness was about 50 nm. Cu-V alloy film deposited at $150^{\circ}C$. XRD, AFM, Hall measurement system, and AES were used to analyze this work. For the barrier formation, annealing temperature was 300, 400, $500^{\circ}C$ (1 hour). Barrier thermal stability was tested by I-V(leakage current) and XRD analysis after 300, 500, $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However vanadium-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Therefore thermal stability of vanadium-based diffusion barrier is desirable for copper interconnection.

• 한국정보통신학회논문지
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• 제16권4호
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• pp.759-764
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• 2012

고밀도집적을 위하여 전기도금과 무전해도금법을 적용하여 구리기둥주석범프(CPTB)를 제작하고, 그 특성을 분석하였다. CPTB는 ${\sim}100{\mu}m$의 피치를 갖도록 KM-1250 건식감광필름(DFR)을 사용하여 먼저 구리기둥범프(CPB)를 도금 전착시킨 다음, 구리의 산화억제를 위하여 그 위에 주석을 무전해 도금하였다. 열-압력에 따른 산화효과와 접합특성을 위하여 전기저항계수와 기계적 층밀림 전단강도를 측정하였다. 전기저항계수는 산화두께의 증가에 따라서 증가하였고, 전단강도는 $330^{\circ}C$에서 500 N의 열-압력일 때 최고치를 나타냈다. 시뮬레이션 결과에 따르면, CPTB는 시간이 경과됨에 따라 통전면적의 크기 감소의 결과를 나타냈으며, 그것은 구리의 산화에 의해 크게 영향을 받는 것으로 확인되었다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 추계학술대회
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• pp.726-729
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• 2010

고밀도집적을 위하여 전기도금과 무전해도금법을 적용하여 구리기둥주석범프(CPTB)를 제작하고, 그 특성을 분석하였다. CPTB는 ${\sim}100{\mu}m$의 피치를 갖도록 KM-1250 건식감광필름(DFR)을 사용하여 먼저 구리 기둥범프(CPB)를 도금 전착시킨 다음, 구리의 산화억제를 위하여 그 위에 주석을 무전해 도금하였다. 열-압력에 따른 산화효과와 접합특성을 위하여 전기저항계수와 기계적 층밀림전단강도를 측정하였다. 전기저항계수는 산화두께의 증가에 따라서 증가하였고, 전단강도는 $330^{\circ}C$에서 500 N의 열-압력일 때 최고치를 나타냈다. 시뮬레이션 결과에 따르면, CPTB는 크기 감소의 결과를 나타냈으며, 그것은 구리의 산화에 의해 크게 영향을 받는 것으로 확인되었다.

• 전기화학회지
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• 제2권4호
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• pp.237-241
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• 1999

펄스전착법에 의한 구리박막의 특성과 via hole 충진 특성을 연구하였다. 특히 구리박막의 특성에 미치는 첨가제의 영향을 중점적으로 다루었다. 펄스 전류와 첨가제를 사용하여 전착한 구리박막은 83.4 MPa이하의 낮은 인장응력을 가졌으며 높은 Cu (111) 우선 배향성을 나타냈다. Superfilling에 의해 최고 $0.25{\mu}m, 6: 1$ 정도의 고 종횡비를 가지는 via hole에 결함 없이 성공적으로 충진할 수 있었으며 미세 구조를 관찰한 결과 쌍정에 의한 변형이 일어났음을 알 수 있었다. $500^{\circ}C$에서 1시간 동안 진공열처리를 했을 경우 두께의 $1\~2$배에 달하는 결정립을 가지는 bamboo구조를 나타냈으며 이때 전기비저항은 $1.8\~2.0{\mu}{\Omega}{\cdot}cm$을 나타냈다.