• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.267-270
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• 2003

This paper proposes high performance $8{\times}8$ multiplier using current-mode quaternary logic technique. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion), current-mode quaternary logic full-adder block, quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. Also, this multiplier can easily adapted to binary system by the encoder, the decoder. This circuit is simulated under 0.35um standard CMOS technology, 5uA unit current, and 3.3V supply voltage using Hspice.

• Journal of Aerospace System Engineering
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• v.9 no.1
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• pp.12-18
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• 2015

The inter-conversion between different control laws in flight has a lot of risk. The SWM(Switching Mechanism) including logic and stand-by mode is designed to analyze the transient response of aircraft during inter-conversion between different control laws, based on the in-house software for non-real-time and real-time simulation. The SWM applies the fader logic of TFS(Transient Free Switch) to minimize the transient response of an aircraft during the inter-conversion, and applies the reset '0' type of the stand-by mode to prevent surface saturation due to integrator effect in the disengaged flight control law. The transition time is also important to minimize the objectionable transient response in the inter-conversion, as well as the transition control law design. This paper addresses the results of non-real-time simulation for the characteristics of transient response to different transition time to select the adequate transient time, and the real-time pilot evaluation, using SSWM(Software Switching Mechanism) and HSWM(Hardware Switching Mechanism), which is met for Level 1 flying qualities and assures safety of flight.

• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.285-286
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• 2011

Maximum Power Point Tracker (MPPT) is the big issue in generating power based on Wind Energy Conversion System. In case of unknown turbine characteristic, it is useful to implement MPPT based on fuzzy logic control. This kind of control is able to find the value of duty cycle to meet maximum power point at particular wind speed. There are many methods to develop MPPT based fuzzy logic controls. In this paper, two of the methods are compared both at low and high fluctuating wind speed.

• Journal of Institute of Control, Robotics and Systems
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• v.7 no.12
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• pp.1009-1014
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• 2001

The ladder diagram (LD) for programmable logic controllers (PLCs) ar responsible for much important roles in advance industrial automation. As automated systems become more complex the design procedures of the system become more difficult as well. Hence. the design automation issues based on discrete event models(DEMs) are receiving more attention. One of the popular ways of tackling these problems is employing Petri nets. In this paper, we use the modified automation Petri net(MAPN) to model the manufacturing system and the modified token passing logic (MTPL) method conversion (ECC) algorithm based on the MAPN and the MTPL Finally, an example of the manufacturing system is provided to illustrate the proposed ECC algorithm.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.11
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• pp.753-759
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• 2004

This paper presents a modeling and simulation of a fuzzy controller for maximum power extraction of a grid-connected wind energy conversion system with a link of a rectifier and an inverter. It discusses the maximum power control algorithm for a wind turbine and proposes, in a graphical form, the relationships of wind turbine output, rotor speed, power coefficient, tip-speed ratio with wind speed when the wind turbine is operated under the maximum power control. The control objective is to always extract maximum power from wind and transfer the power to the utility by controlling both the pitch angle of the wind turbine blades and the inverter firing angle. Pitch control method is mechanically complicated, but the control performance is better than that of the stall regulation method. The simulation results performed on MATLAB will show the variation of generator's rotor angle and rotor speed, pitch angle, and generator output.

• Korean Journal of Optics and Photonics
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• v.13 no.2
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• pp.151-154
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• 2002

All-optical OR logic gate is realized by use of gain saturation and wavelength conversion in the semiconductor optical amplifiers (SOA). It is operated by the nonlinearity of the SOA gain and hence to obtain the sufficient gain saturation of the SOA, pump signals are amplified by an Er-doped fiber amplifier (EDFA) at the input of the SOA. The operation characteristics of all-optical OR logic gate are successfully measured at 2.5 Gbit/s.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.1-6
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• 2005

This paper proposes a high performance multiplier using CMOS multiple-valued logic circuits. The multiplier based on the Modified Baugh-Wooley algorithm is designed with current-mode CMOS quaternary logic circuits. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion block), current-mode quaternary logic full-adder block, and quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. This multiplier can easily adapted to the binary system by the encoder and the decoder. This circuit is designed with 0.35um standard CMOS process at 3.3V supply voltage and 5uA unit current. The validity and effectiveness are verified through the HSPICE simulation.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.735-738
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• 1998

To develop an effective virtual prototyping methodology for the PLC(Programmable Logic Controller) based real-time systems, a conversion algorithm from RLL(Relay Ladder Logic) to statechart is presented in this paper. The RLL is the main programming language to represent the operation of the PLC, and the statechart is the most widely used tool in the field of virtual prototyping in order to represent the behaviour of real-time systems. A virtual prototyping for an example case is implemened to evaluate the benefit of the proposed algorithm.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.699-702
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• 2005

This paper describes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit and decoding circuit. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 DEMUX (demultiplexer) was designed using a 0.35um standard CMOS technology. Proposed circuit is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW.