• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.11 no.3
• /
• pp.1425-1440
• /
• 2017

In wireless communications, antenna selection (AS) is a widely used method for reducing comparable cost of multiple RF chains in MIMO systems. As is well known, most of literatures on combining AS with MIMO techniques concern linear modulations such as phase shift keying (PSK) and quadrature amplitude modulation (QAM). The combination of CPM and MIMO has been considered an optimal choice that can improve its capacity without loss of power and spectrum efficiency. The aim of this paper is to investigate joint transmit and receive antenna selection (JTRAS) in CPM MIMO systems. Specifically, modified incremental and decremental JTRAS algorithms are proposed to adapt to arbitrary number of selected transmit or receive antennas. The computational complexity of several JTRAS algorithms is analyzed from the perspective of channel capacity. As a comparison, the performances of bit error rate (BER) and spectral efficiency are evaluated via simulations. Moreover, computational complexity of the JTRAS algorithms is simulated in the end. It is inferred from discussions that both incremental JTRAS and decremental JTRAS perform close to optimal JTRAS in BER and spectral efficiency. In the sense of practical scenarios, adaptive JTRAS can be employed to well tradeoff performance and computational complexity.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.10C
• /
• pp.942-948
• /
• 2003

In this paper, we analyze the performance of multiple trellis coded modulation applied to continuous phase frequency shift keying (MTCM/CPFSK) for the noncoherent receiver without channel state information (CSI) on the interleaved Rician fading channel. In this system, the squared cross-correlation between the received signal and a candidate signal is used as the branch metric of the Viterbi decoder. To obtain the bit error performance of this system, we analyze the approximated pairwise error probability (PEP) and the exact PEP. We also derive the equivalent normalized squared distance (ENSD) and compare it with the ENSD of the noncoherent receiver with perfect CSI. Simulation results are also provided to verify the theoretical performance analysis.

• Journal of Power Electronics
• /
• v.15 no.3
• /
• pp.644-651
• /
• 2015

This paper introduces a novel digital one cycle control (DOCC) boost power factor correction (PFC) converter. The proposed PFC converter realizes the FPGA-based DOCC control approach for single-phase PFC rectifiers without input voltage sensing or a complicated two-loop compensation design. It can also achieve a high power factor and the operation of low harmonic input current ingredients over universal loads in continuous conduction mode. The trailing triangle modulation adopted in this approach makes the acquisition of the average input current an easy process. The controller implementation is based on a boost topology power circuit with low speed, low-resolution A/D converters, and economical FPGA development board. Experimental results demonstrate that the proposed PFC rectifier can obtain a PF value of up to 0.999 and a minimum THD of at least 1.9% using a 120W prototype.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.4 no.2
• /
• pp.417-426
• /
• 2000

In this paper, CE-CPSK(Constant Envelope Continuous Phase Shift Keying) modulated DS/SS(Direct Sequence Spread Spectrum) transceiver with 908 MHz carrier frequency and 1.5 MHz PN clock rate is proposed. To overcome the effect of nun-linear power amplifier, CE-CPSK modulation method which has the constant envelope and continuous phase characteristics is proposed. To analyze the DS/SS receiver performance with respect to code tracking loop, multipath fading channel is characterized as a two-ray Rayleigh fading channel. To compensate the demerit of analog delay locked loop, digital delay locked loop is employed for code tracking loop. Simulation and experimental examination has been carried out in AWGN(Additive White Gaussian Noise) and Rayleigh fading channel environment in order to prove validity of the proposed method.

• Proceedings of the KIEE Conference
• /
• 2007.04a
• /
• pp.286-288
• /
• 2007

In this paper, the fast locking PLL Frequency Synthesizer with low phase noise in a 0.18um CMOS process is presented. Its main application IS for the 915MHz ISM band wireless transponder upon the CPFSK (Continuous Phase Frequency Shift Keying) modulation scheme. Frequency synthesizer, which in this paper, is designed based on self-biased techniques and is independent with processing technology when damping factor and bandwidth fixed to most important parameters as operating frequency ratio, broad frequency range, and input phase offset cancellation. The proposed frequecy synthesizer, which is fully-integrated and is in 320M $^{\sim}$ 960MHz of the frequency range with 10MHz of frequency resolution. And its is implemented based on integer-N architecture. Its power consumption is 50mW at 1.8V of supply voltage and core area is $540{\mu}m$ ${\times}$ $450{\mu}m$. The measured phase noises are -117.92dBc/Hz at 10MHz offset, with low settling time less than $3.3{\mu}s$.

• Journal of Power Electronics
• /
• v.17 no.1
• /
• pp.106-114
• /
• 2017

In this paper, the Selective Harmonic Mitigation-PWM (SHM-PWM) method is used in single-phase and three-phase Cascaded H-Bridge (CHB) inverters in order to fulfill different power quality standards such as EN 50160, CIGRE WG 36-05, IEC 61000-3-6 and IEC 61000-2-12. Non-equal DC link voltages are used to increase the degrees of freedom for the proposed SHM-PWM technique. In addition, it will be shown that the obtained solutions become continuous and without sudden changes. As a result, the look-up tables can be significantly reduced. The proposed three-phase modulation method can mitigate up to the 50th harmonic from the output voltage, while each switch has just one switching in a fundamental period. In other words, the switching frequency of the power switches are limited to 50 Hz, which is the lowest switching frequency that can be achieved in the multilevel converters, when the optimal selective harmonic mitigation method is employed. In single-phase mode, the proposed method can successfully mitigate harmonics up to the 50th, where the switching frequency is 150 Hz. Finally, the validity of the proposed method is verified by simulations and experiments on a 9-level CHB inverter.

• Proceedings of the KIPE Conference
• /
• 2003.11a
• /
• pp.238-243
• /
• 2003

The solar cells should be operated at the maximum power point because its output characteristics are greatly fluctuated on the variation of insolation, temperature and load. The output power of solar cell is DC, therefore it is necessary to install an inverter among electric power converts. The inverter have to supply a sinusoidal current and voltage to the load and the interactive utility line. In the paper, the proposes a photovoltaic system designed with a step up chopper and single phase PWM voltage source inverter. Synchronous signal and control signal was processed by microprocessor for stable modulation. The step up chopper operates in continuous mode by adjusting the duty ratio so that the photovoltaic system tracks the maximum power point of solar cell without any influence on the variation of insolation and temperature because solar cell has typical dropping character. The single phase PWM voltage source inverter consists of complex type of electric power converter to compensate for the defect, that is, solar cell cannot be developed continuously by connecting with the source of electric power, from 10 to $20\%$. The single phase PWM voltage source inverter operates in situation that its output voltage is in same phase with the utility voltage. The inverter supplies an ac power with high factor and low level of harmonics to the load and the utility power system.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.5
• /
• pp.879-886
• /
• 2003

Agile frequency synthesizers are the common device used for commandable, wide-band frequency hopping in frequency-hopped (FH) communications. In this paper, synthesizer phase transient effect and its compensation methods in an FH/FSK(Frequency Hopped Frequency Shift Keying) system are studied. Models for these analysis are developed and resulting performance degradations are computed. The basic PLL is difficult to implement for fast frequency hopping in narrowband radio communication systems. To solve this problem, digital frequency synthesizer/CPM (Continuous Phase Modulation)modulator is proposed. And it's performance is analyzed theoretically. The analysis show that fast frequency hopping is possible in frequency hopping system that use digital frequency synthesizer/CPM modulator.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.18 no.5
• /
• pp.97-102
• /
• 2018

In this paper, W-band Waveform Generator for compact radar has been designed and fabricated. DDS (Direct Digital Synthesizer) is applied to generate CW (Continuous Wave) and FMCW (Frequency Modulation Continuous Wave) waveform at high speed. We designed two LO (Local Oscillator) paths for functions of distance delay and distance tracking tests at the prpposed system without extra test equipment. Two mode selections are provided by switch. It is observed that fabricated waveform generator performs -91 dBc/Hz phase noise at offset 1 kHz and -63.2 dBc spurious. Proposed W-band Waveform Generator is expected to apply for W-band compact radar transceiver module.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.7C
• /
• pp.678-687
• /
• 2003

8SQAM(8-state Superposed Quadrature Amplitude Modulation) being a new modem technique for use in power and bandwidth limited digital communication system generates output signals which have a mか and continuous phase transition and a reduced envelope fluctuation by keeping correlation between amplitudes and phases of two subsequent symbols. Also, 8SQAM signal is free of inter-symbol interference(ISI), and has a compact power spectrum. Accordingly 8SQAM, as compared with a conventional 8PSK, is influenced a little by inter-modulation(IM), inter-symbol interference(ISI) and adjacent channel interference(ACI) in a nonlinearly amplified multi-channel(SCPC-FDMA) environment. In this paper, the performance of 8SQAM system in a nonlinearly amplified multi-channel interference environment is analyzed via computer simulation The simulation result shows that 8SQAM outperforms 8PSK with roll-off value of $\alpha$ = 0.3 by 2.7dB in CNR to maintain BER=1$\times$10$^{-4}$ when input back-off(IBO) of HPA is 1dB and channel space is 41.7% of the data bit rate(i.e., spectral efficiency = 2.40b/s/Hz).