• Tribology and Lubricants
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• 제21권6호
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• pp.256-262
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• 2005

The calculation of bump foil deflection is very important to predict the performance of foil bearings more accurately, because the foil bearings consist of top foil and its elastic foundation usually called bump foil. For the purpose of this, a finite element model considering 3-dimensional structure of the bump foil is developed to calculate the deflection of inter-connected bump. The results obtained from the suggested model are compared and analyzed with those from the previous proposed deflection models. In addition, load capacity of the foil bearings is analyzed by using this model.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2001년도 추계학술대회(한국공작기계학회)
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• pp.91-96
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• 2001

When it is considered that many vehicle rides on the road and ride quality is an important method to evaluate vehicle performance with handling, running-over-bump manoeuvre may be suitable for testing ride quality. In this paper, a computed model has roughly steering system and lumped mass, connected by joint each rigid body, and suspension that has beam elements and has shock absorber as force element to represent nonlinear characteristics. A computer simulations for passing over a bump were made with two velocities. One side of vehicle passed over bump in due consideration of driver's habit that driver is subject to avoid a bad ride quality. On simulation, vertical acceleration, pitch angle and roll angle were measured at the mass center of chassis each case.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2006년도 춘계 학술대회 개요집
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• pp.16-17
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• 2006

We researched by the characteristic of a anisotropic etching of Si wafer and the Si career concerning the flip chip solder bump. Connectors and Anisotropic Conductive Film (ACF) method was already applied to board-to-board interconnection. In place of them, we have focused on board to board interconnection with solder bump by Si carrier, which has been used as Flip chip bonding technology. A major advantage of this technology is that the Flexible Printed Circuit (FPC) is connected in the same solder reflow process with other surface mount devices. This technology can be applied to semiconductors and electronic devices for higher functionality, integration and reliability.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

• 대한기계학회:학술대회논문집
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• 대한기계학회 2000년도 춘계학술대회논문집A
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• pp.873-878
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• 2000

Semiconductor packaging technology is changed rapidly according to the trends of the micro miniaturization of multimedia and information equipment. For I/O limitation and fine pitch limitation, DIP and SOP/QFP are replaced by BGA/CSP. This is one of the surface mount technology(SMT). Solder ball is bumped n the die pad and connected onto mounting board. In ball bump formation, vacuum suction type ball alignment process is widely used, However this type has some problems such as ionization, static electricity and difficulty of fifo(first-input first-out) of solder balls. Seesaw type is reducing these problems and has a structural simplicity and economic efficiency. Ball cartridge velocity and ball aligned plate angle are Important variables to improve the ball alignment Process. In this paper, seesaw-type CSP solder ball loader is developed and the optimal velocity and plate angle are proposed.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2007년 추계학술발표대회 개요집
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• pp.229-231
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• 2007

Recently, 3D-electronic packaging by TSV is in interest. TSV(Through Silicon Via) is a interconnection hole on Si-wafer filled with conducting metal such as Copper. In this research, chips with TSV are connected by electroplated Sn bump without PR. Then chips with TSV are put together and stacked by the methode of Reflow soldering. The stacking was successfully done and had no noticeable defects. By eliminating PR process, entire process can be reduced and makes it easier to apply on commercial production.

• 전자공학회논문지D
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• 제36D권9호
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• pp.1-5
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• 1999

본 논문에서는 플립 칩 기술을 이용한 새로운 형태의 브랜치 라인 커플러를 제안하였다. 제안된 구조는 CPW와 반전된 구조의 마이크로스트립으로 이루어져 있다. CPW는 플립 칩 주기판인 GaAs 기판상에 구성되어졌으며, 반전된 구조의 마이크로스트립으로 이루어져 있다. CPW의 접지면은 마이크로스틀립의 접지면으로 사용되며, 두 전송선로는 솔더 범프를 통해 연결되어 있다. 제안된 구조의 특성은 FDTD로 계산되어졌다. S21과 S31은 -3dB이며, 위상차는 $90^{\circ}$인 일반적인 브랜치라인 커플러와 같은 특성을 보였다. 본 제안된 구조는 플립 칩 기술을 이용한 여러 분야에 이용될 수 있으리라 기대된다.

• 전자공학회논문지SC
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• 제40권4호
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• pp.275-281
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• 2003

0.5㎛ 2중 폴리 CMOS 공정을 이용하여 새로운 뉴럴 오실레이터를 설계, 제작하였다. 제안하는 뉴럴 오실레이터는 트랜스콘덕터 및 캐패시터와 비선형 가변 부성저항으로 이루어진다. 뉴럴 오실레이터의 입력단으로 사용되는 비선형 가변 부성저항은 정귀환의 트랜스콘덕터와 가우시안 분포의 전류전압 특성을 지니는 범프 회로를 이용하여 구현하였다. 또한 SPICE 모의실험을 통하여 제안한 오실레이터의 특성분석 후 집적회로 설계를 실시하였다. 한편 흥분성 및 억제성 시냅스로 연결된 4개의 뉴럴 오실레이터로 간단한 신경회로망을 구성하여 그 특성을 확인하였다. 집적회로로 제작된 뉴럴 오실레이터에 대하여 ± 2.5 V 전원 조건하에서 측정된 결과를 분석하고 모의실험 결과와 비교한다.

• Tribology and Lubricants
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• 제39권2호
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• pp.76-80
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• 2023

This paper describes an experimental investigation of the effect of cooling flow rate on gas foil thrust bearing (GFTB) performance. In a newly developed GFTB test rig, a non-contact type pneumatic cylinder provides static loads to the test GFTB and a high-speed motor rotates a thrust runner up to the maximum speed of 80 krpm. Force sensor, torque arm connected to another force sensor, and thermocouples measures the applied static load, drag torque, and bearing temperature, respectively, for cooling flow rates of 0, 25, and 50 LPM at static loads of 50, 100, and 150 N. The test GFTB with the outer radius of 31.5 mm has six top foils supported on bump foil structures. During the series of tests, the transient responses of the bearing drag torque and bearing temperature are recorded until the bearing temperature converges with time for each cooling flow rate and static load. The test data show that the converged temperature decreases with increasing cooling flow rate and increases with increasing static load. The drag torque and friction coefficient decrease with increasing cooling flow rate, which may be attributed to the decrease in viscosity and lubricant (air) temperature. These test results suggest that an increase in cooling flow rate improves GFTB performance.

• 한국지능시스템학회논문지
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• 제24권5호
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• pp.457-461
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• 2014

생물학적 신경 세포의 모델링을 위한 펄스타입 실리콘 뉴런 회로를 $0.18{\mu}m$ CMOS 공정을 이용하여 반도체 집적회로로 설계하였다. 제안하는 뉴런 회로는 입력 전류신호를 위한 커패시터 입력단과, 출력 전압신호 생성을 위한 증폭단 및 펄스신호 초기화를 위한 MOS 스위치로 구성된다. 전압신호 입력을 전류신호 출력으로 변환하는 기능의 시냅스 회로는 몇 개의 PMOS와 NMOS 트랜지스터로 이루어지는 범프회로를 사용한다. 제안하는 뉴런 모델의 검증을 위하여, 2개의 뉴런과 시냅스가 직렬연결된 뉴런체인을 구성하여 SPICE 모의실험을 실시하였다. 모의실험 결과, 뉴런신호의 생성과 시냅스 전달특성의 정상적인 동작을 확인하였다.