• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.283-288
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• 2008

A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation ($IM_3$) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using $0.18-{\mu}m$ technology. The LNA achieved +10.2 dBm IIP3 with 13.7 dB gain and 1.68 dB NF at 2 GHz consuming 11.8 mA from a 1.8-V supply. It shows IIP3 improvement by 6.6 dB over the conventional cascode LNA without the linearizing circuit.

• Journal of information and communication convergence engineering
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• v.13 no.3
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• pp.180-188
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• 2015

As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/µm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/µm.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.190-195
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• 2015

The detection of single nucleotide polymorphisms (SNPs) caused of mutant or genetic diseases is important to diagnosis and medicine. There are many methods have been proposed to detect SNPs. However the detection of SNPs is difficulty, because the difference of energy between complementary DNA (cDMA) and SNPs is very small. In this work, we detect the SNPs using field-effect transistors (FETs) which based on the detection of negative charge of DNA. We bias -0.3 V on the drain-source electrode at the target DNA hybridization process. The efficiency of hybridization and the amplitude of signal decrease by repulsive force between negative charge of DNA and negative bias on the electrode. However, the sensitivity of SNPs increases about 5 times from 1.7 mV to 8.7 mV.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.382-383
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• 2013

Gate-controlled spin-orbit interaction parameter is a key factor for developing spin-Field Effect Transistor (Spin-FET) in a quantum well structure because the strength of the spin-orbit interaction parameter decides the spin precession angle [1]. Many researches show the control of spin-orbit interaction parameter in n-type quantum channels, however, for the complementary logic device p-type quantum channel should be also necessary. We have calculated the spin-orbit interaction parameter and the effective mass using the Shubnikov-de Haas (SdH) oscillation measurement in a GaSb two-dimensional hole gas (2DHG) structure as shown in Fig 1. The inset illustrates the device geometry. The spin-orbit interaction parameter of $1.71{\times}10^{11}$ eVm and effective mass of 0.98 $m^0$ are obtained at T=1.8 K, respectively. Fig. 2 shows the gate dependence of the spin-orbit interaction parameter and the hole concentration at 1.8 K, which indicates the spin-orbit interaction parameter increases with the carrier concentration in p-type channel. On the order hand, opposite gate dependence was found in n-type channel [1,2]. Therefore, the combined device of p- and n-type channel spin transistor would be a good candidate for the complimentary logic device.

• Transactions on Electrical and Electronic Materials
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• v.12 no.6
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• pp.262-266
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• 2011

A simulation study of a current-mode direct current (DC)-DC boost converter is presented in this paper. This converter, with a fully-integrated power module, is implemented by using bipolar complementary metal-oxide semiconductor (BiCMOS) technology. The current-sensing circuit has an op-amp to achieve high accuracy. With the sense metal-oxide semiconductor field-effect transistor (MOSFET) in the current sensor, the sensed inductor current with the internal ramp signal can be used for feedback control. In addition, BiCMOS technology is applied to the converter, for accurate current sensing and low power consumption. The DC-DC converter is designed with a standard 0.35 ${\mu}m$ BiCMOS process. The off-chip inductor-capacitor (LC) filter is operated with an inductance of 1 mH and a capacitance of 12.5 nF. Simulation results show the high performance of the current-sensing circuit and the validity of the BiCMOS converter. The output voltage is found to be 4.1 V with a ripple ratio of 1.5% at the duty ratio of 0.3. The sensing current is measured to be within 1 mA and follows to fit the order of the aspect ratio, between sensing and power FET.