• 농업과학연구
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• 제23권2호
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• pp.285-300
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• 1996

This study is aimed to provide data of low-input rice cultivation for agricultural policy, to reveal the problems of low-input cultivation through comparing the economic result of low-input cultivation with the common one, to search for solution or mitigation of the problems of low-input cultivation, and to forecast the future prospect of low-input rice cultivation. The following were the results obtained from the survey and analysis. The working hours per 10a inputted 45.4 hours which is 32% more than 34.5 hours of common cultivation. Yield per 10a was 355kg which was 101kg less than 456kg of common cultivation. But the farm received price per kg was 1,984.9 won which was 547.9 won more than 1,436.5 won of common cultivation. Gross receipts per 10a was 704,438 won which was higher than 655,044 won of common cultivation, and management cost was 230,820 won which slightly higher than 188,157 won of common cultivation. Consequently, the income of low-input rice cultivation was 473,617 won which somewhat exceed to 466,887 won of common cultivation.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2003년도 추계종합학술대회
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• pp.373-376
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• 2003

본 논문은 고성능 공통 입력버퍼를 가지는 패킷 스위치 패브릭을 위한 새로운 3차원 라운드로빈 스케줄러에 관한 연구이다. 본 논문에서 제안된 스케줄러는 각 입력 버퍼에서 각 출력 큐를 독립적으로 관리하는 분산형 공통 버퍼를 가지는 스위치 패브릭구조에서 고속으로 동작하는 스케줄러이다. 제안된 스케줄러는 M 개의 각 공통 입력 버퍼가 K개의 입력 및 출력 포트를 가지고 N 개의 가상 출력 큐를 관리하고 $K\geq$M (K$\leq$M)일 때 매 K(M) 사이클 마다 MxK 개의 가상 출력 큐들이 목적 출력포트로 패킷을 전송할 수 있도록 스케줄링한다. 대량 병렬 스케줄링 구조를 이용하여 대용량의 스위칭 포트를 가지는 고성능 스위치 패브릭에의 고속 응용을 지원한다.

• 전력전자학회논문지
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• 제27권2호
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• pp.85-91
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• 2022

This study proposes a high efficiency bridgeless Power Factor Correction (PFC) converter with improved common mode noise characteristics. Conventional PFC has limitations due to low efficiency and enlarged heat sink from considerable conduction loss of bridge diode. By applying a Common Mode (CM) coupled inductor, the proposed bridgeless PFC converter generates less conduction loss as only a small magnetizing current of the CM coupled inductor flows through the input diode, thereby reducing or removing heat sink. The input diode is alternately conducted every half cycle of 60 Hz AC input voltage while a negative node of AC input voltage is always connected to the ground, thus improving common mode noise characteristics. With the aim to improve switching loss and reverse recovery of output diode, the proposed circuit employs Critical Conduction Mode (CrM) operation and it features a simple Zero Current Detection (ZCD) circuit for the CrM. In addition, the input current sensing is possible with the shunt resistor instead of the expensive current sensor. Experimental results through 480 W prototype are presented to verify the validity of the proposed circuit.

• 제어로봇시스템학회논문지
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• 제17권9호
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• pp.851-856
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• 2011

In this paper, the fuzzy output-feedback controller is addressed for a discrete-time nonlinear interconnected systems with common input. The nonlinear interconnected system is represented by a T-S (Takagi-Sugeno) fuzzy model. Based on T-S fuzzy interconnected system, the fuzzy output-feedback controller is designed with common input. The stability condition of the closed-loop system is represented to the LMI (Linear Matrix Inequality) form. PEMFC model is given to show the verification of the controller discussed throughout the paper.

• Journal of Power Electronics
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• 제12권3호
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• pp.439-447
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• 2012

In this paper, an input-series auxiliary power supply scheme is proposed, which is suitable for high input voltage and multiple-output applications. The power supply scheme is based on a two-transistor forward topology, all of the series modules have a common duty ratio, all the switches are turned on and off simultaneously, and the whole circuit has a single power transformer. It does not require an additional controller but still achieves efficient input voltage sharing (IVS) for each series module through its inherent transformer-integration strategy. The IVS process of this power supply scheme is analyzed in detail and the design considerations for the related parameters are given. Finally, a 100W multiple-output auxiliary power supply prototype is built, and the experimental results verify the feasibility of the proposed scheme and the validity of the theoretical analysis.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.400-402
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• 2008

A new interleaved forward converter, adopting series-input parallel-output structure with a common transformer reset circuit, is proposed in this paper. Series-input structure distributes the voltage stress on switches, which makes it suitable for high input voltage application. Paralleling output stage with an interleaving technique enables the circuit handle large output current and reduces filter size. In addition, since two forward converters share one active-clamp circuit for the transformer reset, its primary structure is simplified. All these features make the proposed converter promising for high input voltage applications with high efficiency and simple structure.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.137-140
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• 2001

This paper shows an asynchronous comparator circuit for 1.2Gbps signal receiver that converts 1.2Gbps data rate input signals with less than 100㎷ swing to on-chip CMOS compatible voltage levels in a 0.35${\mu}{\textrm}{m}$ CMOS process. Folded-cascode nMOS input stage with source-coupled pMOS input stage cover rail-to-rail input common-mode range. Drastic gain-bandwidth increment due to gain-boosting stage with positive-feedback latch as well as wide input common-mode range make designed circuit be suitable for a fully differential signal receiver. HSPICE simulation results show that worst-case sensitivity is less than 20㎷ and maximum propagation delay is 640-psec. And also we verified 3.97㎽ power consumption with 150㎷ differential swing amplitude at 1.2Gbps.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.567-570
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• 2002

The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.

• 전력전자학회논문지
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• 제26권6호
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• pp.446-453
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• 2021

This paper proposes enhanced single-phase pulse width modulation buck, boost, and buck-boost type ac-ac converters. The proposed converters, where input and output voltages share a common ground, require no isolated voltage sensor and have no leakage current problem. The commutation problem is solved with series-connected switching cell structures without using an additional RC snubber. In addition, with the use of the polarity of input voltage, switching patterns are determined so that the inductor currents can flow through switching devices during all operational modes. Two switches are always turned on during a half-period of the input voltage; thus, the switching loss is significantly reduced. Detailed analysis and experimental results are provided to verify the performance of the proposed converter.

• 대한전자공학회논문지SP
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• 제41권5호
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• pp.283-290
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• 2004

이 논문에서는 MPEG audio 알고리즘의 필터뱅크를 덧셈을 사용하여 저전력으로 구현할 수 있는 구조를 제안하였다. 제안된 구조는 CSD(Canonic Signed Digit) 형의 계수를 사용하며, 입력신호 샘플을 최대로 공유함으로서 사용되는 덧셈기의 수를 최소화하였다. 제안된 구조는 알고리즘에서 사용된 공통입력 공유, 선형위상 대칭 필터계수를 이용한 공유, 공통입력을 이용한 블록 공유, CSD 형의 계수와 공통패턴 공유를 통하여 사용되는 덧셈의 수를 최소화할 수 있음을 보였다. Verilog-HDL 코딩을 통하여 시뮬레이션을 수행한 결과, 제안된 구조는 기존의 곱셈기 구조의 구현면적과 비교하여 60.3%를 감소시킬 수 있음을 보였다. 또한 제안된 구조의 전력소모는 곱셈기 구조와 비교하여 93.9%를 감소시킬 수 있음을 보였다. 따라서 고속의 곱셈기가 내장된 DSP 프로세서를 사용하지 않고도, Arithmetic Unit나 마이크로 프로세서를 사용하여 효과적으로 MPEG audio 필터뱅크를 구현할 수 있음을 보였다.