• Korean Journal of Agricultural Science
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• v.23 no.2
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• pp.285-300
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• 1996

This study is aimed to provide data of low-input rice cultivation for agricultural policy, to reveal the problems of low-input cultivation through comparing the economic result of low-input cultivation with the common one, to search for solution or mitigation of the problems of low-input cultivation, and to forecast the future prospect of low-input rice cultivation. The following were the results obtained from the survey and analysis. The working hours per 10a inputted 45.4 hours which is 32% more than 34.5 hours of common cultivation. Yield per 10a was 355kg which was 101kg less than 456kg of common cultivation. But the farm received price per kg was 1,984.9 won which was 547.9 won more than 1,436.5 won of common cultivation. Gross receipts per 10a was 704,438 won which was higher than 655,044 won of common cultivation, and management cost was 230,820 won which slightly higher than 188,157 won of common cultivation. Consequently, the income of low-input rice cultivation was 473,617 won which somewhat exceed to 466,887 won of common cultivation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.373-376
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• 2003

This paper presents a new, three-dimensional round-robin scheduler that provides high throughput and fair across in an advanced input-queued packet switch using shared input buffers. We consider an architecture in which each input port group shares a common buffer and maintains a separate queue for each output, which is ratted the distributed common input buffer switch. In an NxN switch, our scheduler determines which queue in the total MxN input queues is served during each time slot where M is the number of common buffers. We suppose that each common buffer has K input ports and K output ports, and manages N output queues. The 3DRR scheduler determines MxK queues in every K(M) cycle when $K\geq$M (K$\leq$M), and provides massively parallel processing for the applications of high-speed switches with a large number of ports. The 3-DRR scheduler can be implemented using duplicated simple logic components allowing very high-speed implementation.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.2
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• pp.85-91
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• 2022

This study proposes a high efficiency bridgeless Power Factor Correction (PFC) converter with improved common mode noise characteristics. Conventional PFC has limitations due to low efficiency and enlarged heat sink from considerable conduction loss of bridge diode. By applying a Common Mode (CM) coupled inductor, the proposed bridgeless PFC converter generates less conduction loss as only a small magnetizing current of the CM coupled inductor flows through the input diode, thereby reducing or removing heat sink. The input diode is alternately conducted every half cycle of 60 Hz AC input voltage while a negative node of AC input voltage is always connected to the ground, thus improving common mode noise characteristics. With the aim to improve switching loss and reverse recovery of output diode, the proposed circuit employs Critical Conduction Mode (CrM) operation and it features a simple Zero Current Detection (ZCD) circuit for the CrM. In addition, the input current sensing is possible with the shunt resistor instead of the expensive current sensor. Experimental results through 480 W prototype are presented to verify the validity of the proposed circuit.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.9
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• pp.851-856
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• 2011

In this paper, the fuzzy output-feedback controller is addressed for a discrete-time nonlinear interconnected systems with common input. The nonlinear interconnected system is represented by a T-S (Takagi-Sugeno) fuzzy model. Based on T-S fuzzy interconnected system, the fuzzy output-feedback controller is designed with common input. The stability condition of the closed-loop system is represented to the LMI (Linear Matrix Inequality) form. PEMFC model is given to show the verification of the controller discussed throughout the paper.

• Journal of Power Electronics
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• v.12 no.3
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• pp.439-447
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• 2012

In this paper, an input-series auxiliary power supply scheme is proposed, which is suitable for high input voltage and multiple-output applications. The power supply scheme is based on a two-transistor forward topology, all of the series modules have a common duty ratio, all the switches are turned on and off simultaneously, and the whole circuit has a single power transformer. It does not require an additional controller but still achieves efficient input voltage sharing (IVS) for each series module through its inherent transformer-integration strategy. The IVS process of this power supply scheme is analyzed in detail and the design considerations for the related parameters are given. Finally, a 100W multiple-output auxiliary power supply prototype is built, and the experimental results verify the feasibility of the proposed scheme and the validity of the theoretical analysis.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.400-402
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• 2008

A new interleaved forward converter, adopting series-input parallel-output structure with a common transformer reset circuit, is proposed in this paper. Series-input structure distributes the voltage stress on switches, which makes it suitable for high input voltage application. Paralleling output stage with an interleaving technique enables the circuit handle large output current and reduces filter size. In addition, since two forward converters share one active-clamp circuit for the transformer reset, its primary structure is simplified. All these features make the proposed converter promising for high input voltage applications with high efficiency and simple structure.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.137-140
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• 2001

This paper shows an asynchronous comparator circuit for 1.2Gbps signal receiver that converts 1.2Gbps data rate input signals with less than 100㎷ swing to on-chip CMOS compatible voltage levels in a 0.35${\mu}{\textrm}{m}$ CMOS process. Folded-cascode nMOS input stage with source-coupled pMOS input stage cover rail-to-rail input common-mode range. Drastic gain-bandwidth increment due to gain-boosting stage with positive-feedback latch as well as wide input common-mode range make designed circuit be suitable for a fully differential signal receiver. HSPICE simulation results show that worst-case sensitivity is less than 20㎷ and maximum propagation delay is 640-psec. And also we verified 3.97㎽ power consumption with 150㎷ differential swing amplitude at 1.2Gbps.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.567-570
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• 2002

The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.6
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• pp.446-453
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• 2021

This paper proposes enhanced single-phase pulse width modulation buck, boost, and buck-boost type ac-ac converters. The proposed converters, where input and output voltages share a common ground, require no isolated voltage sensor and have no leakage current problem. The commutation problem is solved with series-connected switching cell structures without using an additional RC snubber. In addition, with the use of the polarity of input voltage, switching patterns are determined so that the inductor currents can flow through switching devices during all operational modes. Two switches are always turned on during a half-period of the input voltage; thus, the switching loss is significantly reduced. Detailed analysis and experimental results are provided to verify the performance of the proposed converter.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.5
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• pp.283-290
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• 2004

In this paper, a low-power structure for 512 tap FIR filter in MPEG audio algorithm is proposed. By using CSD(Canonic Signed Digit) form filter coefficients and maximum sharing of input signal sample, it is shown that the number of adders of proposed structure can be minimized. To minimize the number of adders, the proposed structure utilizes the 4 steps of sharing, i.e., common input sharing, linear phase symmetric filter coefficient sharing, block sharing for common input, and common sub-expression sharing. Through Verilog-HDL coding, it is shown that reduction rates in the implementation area and relative power consumption of the proposed structure are 60.3% and 93.9% respectively, comparison to those of the conventional multiplier structure.