• Journal of Information Processing Systems
• /
• v.17 no.1
• /
• pp.191-202
• /
• 2021

In an Internet of Things (IoT)-configured system, each device executes on-chip software. Recent IoT devices require fast execution time of complex services, such as analyzing a large amount of data, while maintaining low-power computation. As service complexity increases, the service requires high-performance computing and more space for embedded space. However, the low performance of IoT edge devices and their small memory size can hinder the complex and diverse operations of IoT services. In this paper, we propose a remote on-demand software code execution unit using the cloudification of on-chip code memory to accelerate the program execution of an IoT edge device with a low-performance processor. We propose a simulation approach to distribute remote code executed on the server side and on the edge side according to the program's computational and communicational needs. Our on-demand remote code execution unit simulation platform, which includes an instruction set simulator based on 16-bit ARM Thumb instruction set architecture, successfully emulates the architectural behavior of on-chip flash memory, enabling embedded devices to accelerate and execute software using remote execution code in the IoT environment.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.3
• /
• pp.427-435
• /
• 2015

This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.8
• /
• pp.2473-2483
• /
• 2000

In this paper, The turbo code is used to effectively remove noise which is generated on the image communication channel. Turbo code had excellent decoding performance. However, it had limitations for real time communication because of the system complexity and time delay in decoding procedure. To overcome this problem, this paper proposed a new SRI(Semi Random Interleaved algorithm, which decrease the time delay, when the image data, which reduced the interleaver size of turbo code encoder and decoder, transmitted. The SRI algorithm was composed of 0.5 interleaver size from input frame sequence. When the data inputs in interleaver, the data recorded by row such as block interleaver. But, When the data read in interleaver, the data was read by randomly and the next data located by the just address simultaneously. Therefore, the SRI reduced half-complexity when it was compared with pre-existing method such as block, helical, random interleaver. The image data could be the real time processing when the SRI applied to turbo code.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.8
• /
• pp.28-38
• /
• 2013

In this paper, we propose a improved turbo equalizer which generates a feedback signal through a simple calculation to improve performance in single carrier system with the LMS(least mean square) algorithm based equalizer and LDPC(low density parity check) codes. LDPC codes can approach the Shannon limit performance closely. However, computational complexity of LDPC codes is greatly increased by increasing the repetition of the LDPC codes and using a long parity check matrix in harsh environments. Turbo equalization based on LDPC code is used for improvement of system performance. In this system, there is a disadvantage of very large amount of computation due to the increase of the repetition number. To less down the amount of this complicated calculation, The proposed improved turbo equalizer adjusts the adoptive equalizer after the soft decision and the LDPC code. Through the simulation results, it's confirmed that performance of improved turbo equalizer is close to the SISO-MMSE(soft input soft output minimum mean square error) turbo equalizer based on LDPC code with the smaller amount of calculation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.8A
• /
• pp.598-606
• /
• 2003

In this paper, we analyze the performance of the PCM cell search algorithm proposed for fast cell search of WCDMA systems. In order to improve both performance and complexity of the cell search algorithm standardized for WCDMA systems the PCM scheme uses a group of the polarization codes produced by a Gold code generator. The PCM scheme only uses one synchronization channel since the polarization codes modulated on P-SCH can replace the RS codes of S-SCH. Thus, the PCM reduces the BS's transmission power since only one synchronization channel can be used, and it can also reduce the complexity of receiver as compared with the conventional one. In this paper, by defining a numerical model, we analyze the performance of the PCM cell search algorithm in terms of detection probability and mean acquisition time. Consequently, we could demonstrate that the PCM cell search algorithm is superior to the standard WCDMA cell search algorithm.

• Journal of the Korea Society for Simulation
• /
• v.18 no.3
• /
• pp.1-11
• /
• 2009

This paper illustrates a case study of PLC logic simulation in a car manufacturing system. It was developed to simulate and verify PLC control program for automobile panel AS/RS. Because car models become varied, the complexity of supply problem is increasing in the car manufacturing system. To cope with this problem, companies use the AS (automated storage) and RS (retrieval system) but it has logical complexity. Industrial automated process uses PLC code to control the AS/RS, however control information and control codes (PLC code) are difficult to understand. This paper suggests a PLC simulation environment, using 3D models and PLC code with realistic data. Data used in this simulation is based on realistic 3D model and I/O model, using actual size and PLC signals, respectively. The environment is similar to a real factory; users can verify and test the PLC code using this simulation before the implementation of AS/RS. Proposed simulation environment can be used for test run of AS/RS to reduce implementation time and cost.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.6 no.1
• /
• pp.20-26
• /
• 2011

In this paper, we propose an efficient algorithm for reducing the complexity of LDPC code decoding by using node monitoring (NM) and Piecewise Linear Function Approximation (NP). This NM algorithm is based on a new node-threshold method, and the message passing algorithm. Piecewise linear function approximation is used to reduce the complexity for more. This algorithm was simulated in order to verify its efficiency. Simulation results show that the complexity of our NM algorithm is reduced to about 20%, compared with thoes of well-known method.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.10 no.11
• /
• pp.1231-1238
• /
• 2015

In this paper, we proposed an efficient algorithm using Node monitoring (NM) and Piecewise Linear Function Approximation(: NP) for reducing the complexity of LDPC code decoding. Proposed NM algorithm is based on a new node-threshold method together with message passing algorithm. Piecewise linear function approximation is used to reduce the complexity of the algorithm. This new algorithm was simulated in order to verify its efficiency. Complexity of our new NM algorithm is improved to about 20% compared with well-known methods according to simulation results.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
• /
• 1991.11a
• /
• pp.40-48
• /
• 1991

McEliece 공개키 암호체계에 대한 새로운 암호해독적 공격이 제시되어진다. 기존의 암호해독 algorithm이 exponential-time의 complexity를 가지는 반면, 본고에서 제시되어지는 algorithm은 polynomial-time의 complexity를 가진다. 모든 linear codes에는 systematic generator matrix가 존재한다는 사실이 본 연구의 동기가 된다. Public generator matrix로부터, 암호해독에 사용되어질 수 있는 새로운 trapdoor generator matrix가 Gauss-Jordan Elimination의 역할을 하는 일련의 transformation matrix multiplication을 통해 도출되어진다. 제시되어지는 algorithm의 계산상의 complexity는 주로 systematic trapdoor generator matrix를 도출하기 위해 사용되는 binary matrix multiplication에 기인한다. Systematic generator matrix로부터 쉽게 도출되어지는 parity-check matrix를 통해서 인위적 오류의 수정을 위한 Decoding이 이루어진다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.7
• /
• pp.1419-1426
• /
• 1997

A new SCEE(Syndrome Check Error Estimation) decoding method for convolutional code and concatenated SCEE/RS (Reed-Solomon) conding scheme are proposed. First, we describe the operation of the decoding steps in the proposed algorithm. Then deterministic values on the decoding operation are drived when some combination of predecoder-reencoder is used. Computer simulation results show that the compuatational complexity of the proposed SCEE decoder is significantly reduced compared to that of conventional Viterbi-decoder without degratation of the $P_{e}$ performance. Also, the concatenated SCEE/RS decoder has almost the same complexity of a RS decoder and its coding gain is higher than that of soft decision Viterbi or RS decoder respectively.