• Journal of Information Processing Systems
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• v.16 no.3
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• pp.541-556
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• 2020

Wireless networks have become integral to society as they provide mobility and scalability advantages. However, their disadvantage is that they cannot control the media, which makes them vulnerable to various types of attacks. One example of such attacks is the evil twin access point (AP) attack, in which an authorized AP is impersonated by mimicking its service set identifier (SSID) and media access control (MAC) address. Evil twin APs are a major source of deception in wireless networks, facilitating message forgery and eavesdropping. Hence, it is necessary to detect them rapidly. To this end, numerous methods using clock skew have been proposed for evil twin AP detection. However, clock skew is difficult to calculate precisely because wireless networks are vulnerable to noise. This paper proposes an evil twin AP detection method that uses a multiple-feature-based machine learning classification algorithm. The features used in the proposed method are clock skew, channel, received signal strength, and duration. The results of experiments conducted indicate that the proposed method has an evil twin AP detection accuracy of 100% using the random forest algorithm.

• Biomedical Science Letters
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• v.11 no.4
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• pp.493-501
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• 2005

Circadian rhythms, time on a scale of about 24 hours, are present in a number of organisms including animals, plants, and bacteria. The control of the biochemical, physiological and behavioral processes is regulated by endogenous clocks in the suprachiasmatic nucleus (SCN). At the core of this timing mechanism is molecular machinery that are present both in the brain and in the peripheral tissues throughout the body, and even in a single cultured cell. In this study, we performed two-dimensional gel electrophoresis to figure out any correlation between protein expression patterns and the requirement of two canonical clock proteins, either mPER1 or mPER2, by comparing global protein expression profiles in livers from wildtype or mPer1/mPer2 double mutant mice. We could identify several differentially expressed protein candidates with respect to time and genotypes. Further analysis of these candidate proteins in detail in vivo will lead us to the better understanding of how circadian clock functions in mammals.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.188-193
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• 2003

This paper describes a novel burst-mode clock and data recovery (CDR) circuit which can be used for 622Mbps burst mode applications. The CDR circuit is basically a phase locked loop (PLL) having two phase detectors (PDs), one for the reference clock and the other for the NRZ data, whose operations are controlled by an external control signal. This CDR was fabricated in a 1-poly 5-metal $0.25{\;}\mu\textrm{m}$ CMOS technology. Jitter generation, burst/continuous mode data receptions were tested. Operational frequency range is 320Mhz~720Mhz and BER is less than 1e-12 for PRBS31 at 622Mhz. For the same data sequence, the extracted clock jitter is less than 8ps rms. Power consumption of 100mW was measured without I/O circuits.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1563-1566
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• 2002

A 16-bit adiabatic datapath for micro-power RISC processor is designed. The datapath is composed of a 3-read and 1-write multi-port adiabatic register file and an arithmetic and logic unit. A four-phase clock generator is also designed to provide supply clocks fer adiabatic circuits and the driving capability control scheme is proposed. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on efficient charge recovery logic(ECRL) and are implemented using a 0.35 fm CMOS technology. Functional and energy simulation is carried out to show the feasibility of adiabatic datapath. Simulation results show that the power consumption of the adiabatic datapath including supply clock generator is reduced by a factor of 1.4∼1.5 compared to that of the conventional CMOS.

• Progress in Superconductivity and Cryogenics
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• v.8 no.2
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• pp.17-19
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• 2006

A novel clock distribution technique for pipelined-RSFQ logics using variable Bias Currents of JTLs as delay-medium is newly proposed. RSFQ logics consist of several logic gates or blocks connected in a pipeline structure. And each block has variable delay difference. In the structure, this clock distribution method generates a set of clock signals for each logic blocks with suitable corresponding delays. These delays, in the order of few to tens of pS, can be adjusted through controlling bias current of JTL of delay medium. While delays with resistor value and JJ size are fixed at fabrication stage, delay through bias current can be controlled externally, and thus, is heavily investigated for its range as well as correct operation within current margin. Possible ways of a standard delay library with modular structure are sought for further modularizing Pipelined-RSFQ applications. Simulations and verifications are done through WRSpice with Hypres 3-um process parameters.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.309-314
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• 2006

In general DGPS system, the correction message is transferred to users by wireless modem. To cover wide area, many DGPS station should be needed. And DGPS users must have a wireless modem that is not necessary in standalone GPS. But SBAS users don't need a wireless modem to receive DGPS corrections because SBAS correction message is transmitted from the GEO satellite by L1 frequency band. SBAS signal is generated in the GUS(Geo Uplink Subsystem) and uplink to the GEO satellite. This uplink transmission process causes two problems that are not existed in GPS. The one is a time delay in the uplink signal. The other is an ionospheric problem on uplink signal, code delay and carrier phase advance. These two problems cause ranging error to user. Another critical ranging error factor is clock synchronization. SBAS reference clock must be synchronized with GPS clock for an accurate ranging service. The time delay can be removed by close loop control. We propose uplink ionospheric error correcting algorithm for C/A code and carrier. As a result, the ranging accuracy increased high. To synchronize SBAS reference clock with GPS clock, I reviewed synchronization algorithm. And I modified it because the algorithm didn't consider doppler that caused by satellites' dynamics. SBAS reference clock synchronized with GPS clock in high accuracy by modified algorithm. We think that this paper will contribute to basic research for constructing satellite based DGPS system.

• Journal of Life Science
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• v.33 no.9
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• pp.730-735
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• 2023

In the past decade, numerous studies have been carried out to quantify aging with the help of artificial intelligence. Using DNA methylation data, various models have been developed; these are commonly called epigenetic clocks. Epigenetic age acceleration is usually associated with disease conditions. Schizophrenia is a mental illness associated with severe mental and physical stress. This disease leads to high mortality and morbidity rates in young people compared with other psychological disorders. In the past, the research community considered this disease to be related to the accelerated aging hypothesis. In the current study, we wanted to investigate the epigenetic age acceleration changes in schizophrenia patients to obtain epigenetic insights into the disease. To measure the epigenetic age acceleration, we used two different DNA methylation clock models, namely, Horvath clock and Epi clock, as these are pan-tissue models. We utilized 450k array data compatible with both clocks. We found a slower epigenetic acceleration in the patients' samples when we used the Epi clock. We further analyzed the differentially methylated CpG sites between the control and cases and performed pathway enrichment analysis. We found that most of the CpGs are involved in neuronal processes.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.7
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• pp.1005-1014
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• 1990

This paper proposes the control unit of a 32-bit high-performance RISC type microprocessor. This control unit controls the whole data path of target processor and on chip instruction/data caches in 4-stage pipelined scheme. For the improvement of speed, large parts of data path and control unit are designed by domino-CMOS and hard-wired circuit technology. First, in this paper, target processor's instruction set and data path are defined, and next, all signals needed to control the data path are analyzed. The decoder of control unit and clock generated logic block are implemented in DCAL(Dynamic CMOS Array Logic) with modified clock scheme for the purpose of speed up and supporting RISC processor's pipelined architecture efficiently.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.568-576
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• 2017

This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.

• Earthquakes and Structures
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• v.22 no.1
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• pp.65-82
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• 2022

This paper presents a structural performance assessment of a historical masonry clock tower both using numerical and experimental process. The numerical assessment includes developing of finite element model with considering different types of soil-structure interaction systems, identifying the numerical dynamic characteristics, finite element model updating procedure, nonlinear time-history analysis and evaluation of seismic performance level. The experimental study involves determining experimental dynamic characteristics using operational modal analysis test method. Through the numerical and experimental processes, the current structural behavior of the masonry clock tower was evaluated. The first five experimental natural frequencies were obtained within 1.479-9.991 Hz. Maximum difference between numerical and experimental natural frequencies, obtained as 20.26%, was reduced to 4.90% by means of the use of updating procedure. According to the results of the nonlinear time-history analysis, maximum displacement was calculated as 0.213 m. The maximum and minimum principal stresses were calculated as 0.20 MPa and 1.40 MPa. In terms of displacement control, the clock tower showed only controlled damage level during the applied earthquake record.