• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.1-12
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• 2020

Handling precise timing in high-speed transceivers has always been a primary design target to achieve better performance. Many different approaches have been tried, and one of those is utilizing the beneficial nature of injection locking. Though the phenomenon was not intended for building integrated circuits at first, its coupling effect between neighboring oscillators has been utilized deliberately. Consequently, the dynamics of the injection-locked oscillator (ILO) have been explored, starting from R. Adler. As many aspects of the ILO were revealed, further studies followed to utilize the technique in practice, suggesting alternatives to the conventional frequency syntheses, which tend to be complicated and expensive. In this review, the historical analysis techniques from R. Adler are studied for better comprehension with proper notation of the variables, resulting in numerical results. In addition, how the timing jitter or phase noise in the ILO is attenuated from noise sources is presented in contrast to the clock generators based on the phase-locked loop (PLL). Although the ILO is very promising with higher cost effectiveness and better noise immunity than other schemes, unless correctly controlled or tuned, the promises above might not be realized. In order to present the favorable conditions, several strategies have been explored in diverse applications like frequency multiplication, data recovery, frequency division, clock distribution, etc. This paper reviews those research results for clock multiplication and data recovery in detail with their advantages and disadvantages they are referring to. Through this review, the readers will hopefully grasp the overall insight of the ILO, as well as its practical issues, in order to incorporate it on silicon successfully.

• Transactions of the Society of Information Storage Systems
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• v.1 no.1
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• pp.34-41
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• 2005

We report some recent results in the rewritable Blu-ray Disc with enhanced overwrite cyclability by using the growth dominant eutectic based Ge(Sb70Te30)+Sb recording layer, GeN interface layer and write strategy optimization. We have developed phase-change optical media with appropriate write strategy for 36(i.e., 1X)-72Mbps(i.e., 2X) dual speed Blu-ray Disc system and fur the future high speed optical data storage. For recording layer, eutectic-based Ge(Sb70Te30)+Sb material was used and Sb/Te ratio and Ge content were optimized to obtain proper erasability and archival stability of recorded amorphous marks. The recording layer is wrapped up in GeN interface layers to obtain overwrite cyclability and higher crystallization speed. In addition, we designed appropriate write strategy so called Time-Shifted Multipulse (TSMP) write strategy where starting position of multipulse parts are shined from reference clock. With this write strategy, the jitter characteristics of the disc was improved and we found that leading edge jitter was improved much more than trailing edge jitter in 1X-2X speed recording. Finally, we investigated the higher speed feasibility of 144Mbps(i.e., 4X) by adopting some elemental doping to the eutectic based Ag-In-Sb-Te recording layer and structural optimization of constitution layers in Blu-ray Disc. In the paper, we report the effect of Sn addition for the feasibility of higher speed recording. The addition of Sn shows increases of the crystallization speed of phase change recording layer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.130-134
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• 2008

This paper presents a clock and data recovery(CDR) using a quarter-rate technique. The proposed CDR helps reduce the VCO frequency and is thus advantageous for high speed application. It can achieve a low jitter operation and extend the pull-in range without a reference clock. The CDR consists of a quarter-rate bang-bang type phase detector(PD) quarter-rate frequency detector(QRFD), two charge pumps circuits(CPs), low pass filter(LPF) and a ring voltage controlled oscillator(VCO). The Proposed CDR has been fabricated in a standard $0.18{\mu}m$ 1P6M CMOS technology. It occupies an active area $1{\times}1mm^2$ and consumes 98 mW from a single 1.8 V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.1100-1112
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• 1998

In this paper, a novel method of minimizing the phase error is proposed. A DP-PLL system using this method is implemented and its performacnce is investigated, too. The DP-PLL system detects the phase error between reference clock and locally generated system clock. The phase difference is then reported as a PEV(Phase Error Variation), which is propoced from the delayted n-tap rising dege clock circuit with 5ns resolution in the phase detector. The algorithm is used to track the optimal DAC coefficients, which are adjusted from sample to sample in such a way as to minimize the PEV. The proposed method is found to have remarkable good potential for fast and accurate phase error tracking characteristic. The algorithm shows good performance to supress the low frequency jitter.-ending points, we design new basis functions based on the Legendre polynomial and then transform the error signals with them. When applied to synthetic images such as circles, ellipses and etc., the proposed method provides, in overall, outstanding results in respect to the transform coding gain compared with DCT and DST. And in the case when applied to natural images, the proposed method gives better image quality over DCT and comparable results with DST.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.43-49
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• 2000

We proposed ADD(Alternate Directional Delay) circuit technique as the DLL(Delay Locked Loop) circuits which technique is established the data valid window(tDV) in DDR(Double Data Rate) Synchronous DRAM. This technique could be decrease area-overhead which it could generated bidirectional clock simultaneously using only one delay chain block. In this paper for high speed memory with relatively small size. This technique decreased area-overhead more 2 times than SMD(Synchronous Mirror Delay) technique. ADD technique has 50ps-140ps jitter and the operation frequency has 166MHz-66MHz range.(at 2.5V, TYP. condition)

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.1-6
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• 2002

In this paper, an Analog Flat Panel interface(AFPI) which supports for UXGa(Ultar extended Graphics Array)-Compatible TFT LCD Driver is designed. The Proposed AFPI is composed of 8-b ADC, Automatic Gain Control(AGC), Low-Jitter PLL. In order to obtain a high speed and low power consumption, an efficient architecture of 8-bit ADC is proposed, whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 2, and IR (Interpolating Rate) is 16. We can get high SNDR by adopting distributed track and hold circuits. Also a programmable AGC which is possible to control gain and clamp, and a low-jitter PLL are proposed. The chip has been fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly S-metal n-well CMOS technology. The effective chip area is 3.6mm $\times$ 3.2mm and it dissipates about 602㎽ at 2.5V power supply. The INL and DNL are within $\pm$ 1LSB. The measured SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.860-866
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• 2016

An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur. The prototype chip fabricated in 65-nm CMOS technology achieves a $285-fs_{rms}$ integrated jitter at GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the ILRPLL is -242.4 dB.

• The Journal of the Korea Contents Association
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• v.9 no.7
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• pp.76-85
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• 2009

UWB signal with high resolution capability can be used to estimate ranging and positioning in wireless personal area network. The node works on its local clock and the frequency differences of nodes have serious affects on ranging algorithms estimating locations of mobile nodes. The low rate UWB, IEEE802.15.4a, describes asynchronous two way ranging methods such as TWR and SDS-TWR working without any additional network synchronization, but the algorithms can not eliminate the effect of clock frequency differences. Therefore, the mechanisms to characterize the crystal difference is essential in typical UWB PHY implementations. In high rate UWB, characterizing of crystal offset with tracking loop is not required. But, detection of the clock frequency offset between the local clock and remote clock can be performed if there is little noise induced jitter. In this paper, we complete related ranging equations of high rate UWB based on TWR with relative frequency offset, and analyze a residual error in the ideal equations. We also evaluate the performance of the relative frequency offset algorithm by simulation and analyze the ranging errors according to the number of TWR to compensate coarse clock resolution. The results show that the relative frequency offset compensation and many times of TWR enhance the performance to converge to a limited ranging errors even with coarse clock resolutions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2409-2418
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• 2013

Two frequency synthesizers are proposed to generate a clock for a sub-sampler of an on-chip oscilloscope in this paper. These proposed frequency synthesizers are designed by using a multi-phase delayed-locked loop (DLL)-based phase selector and a fractional-N phase-locked loop (PLL), and they are analyzed by comparing simulation results of each frequency synthesizer. Two proposed frequency synthesizers are designed using a 65-nm CMOS process with a 1V supply and output the clock with the frequency of 121.15 MHz when the frequency of an input clock is 125 MHz. The designed frequency synthesizer using a multi-phase DLL-based phase selector has the area of 0.167 $mm^2$ and the peak-to-peak jitter performance of 2.88 ps when it consumes the power of 4.75 mW. The designed frequency synthesizer using a fractional-N PLL has the area of 0.662 $mm^2$ and the peak-to-peak jitter performance of 7.2 ps when it consumes the power of 1.16 mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1074-1079
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• 1999

A high performance CMOS receiver for 155.52 Mbps STM-1 digital communication has been designed and fabricated. The ASIC operates properly with 155.52 MHz clock frequency in case of the data loss due to some system error such as transmission line open or data transfer fail. Also it operates properly in case the system starts after the power failure or system maintenance. The designed circuit has especially PLL based self oscillation loop which operates on abnormal environment which is added to main oscillation loop. The measured results show that the circuit operates well with 153.52 MHz clock frequency not only on normal environment but also on abnormal environment. Rms jitter of the PLL loop is about 23 ps.