• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1185-1188
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• 2003

This paper describes a design for a 2.5Gb/s serial data link CMOS transceiver based on the InfiniBand$^{TM}$ specification. The transceiver chip integrates data serializer, line driver, Tx PLL, deserializer, clock recovery, and lock detector. The designed transceiver is fabricated in a 0.25 ${\mu}{\textrm}{m}$ CMOS mixed-signal, 1-poly, 5-metal process. The first version chip occupies a 3.0mm x 3.3mm area and consumes 450mW with 2.5V supply. In 2.5 Gbps, the output jitter of transmitter measured at the point over a 1.2m, 50Ω coaxial cable is 8.811ps(rms), 68ps(p-p). In the receiver, VCO jitter is 18.5ps(rms), 130ps(p-p), the recovered data are found equivalent to the transmitted data as expected. In the design for second version chip, the proposed clock and data recovery circuit using linear phase detector can reduce jitter in the VCO of PLL.L.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.512-515
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• 2009

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage ($V_D$) and the optimum clock frequency ($f_c$) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to $31.5{\mu}W$, which was only 2.8% that of a conventional ME processor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.469-471
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• 2022

This paper presents an implementation of a calibration circuit to correct the gain error, DC offset and sampling clock phase error generated in the process of converting digital pixels to analog pixels to drive an analog-driven 4K UHD LCOS panel. The proposed calibration circuit consists of a gain and DC offset adjustment circuit and a sampling clock phase adjustment circuit. The calibration circuit is implemented with an FPGA device, and video amplifiers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.7-13
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• 2009

This paper presents a multi-channel transceiver that achieves a data rate of 3.125Gb/s/ch. The LVDS is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. On the receiver side, a low-power CDR(clock and data recovery) using 1/4-rate clock based on dual-interpolator is proposed. The CDR generates needed additional clocks in each recovery part internally using only inverters. Therefore each part can be supplied with the same number of 1/4-rate clocks from a clock generator as in 1/2-rate clock method. Thus, the reduction of a clock frequency relaxes the speed limitation and lowers power dissipation. The prototype chip is comprised of two channels and was fabricated in a $0.18{\mu}m$ standard CMOS process. The output jitter of transmitter is loops, peak-to-peak(0.31UI) and the measured recovered clock jitter is 47.33ps, peak-to-peak which is equivalent to 3.7% of a clock period. The area of the chip is $3.5mm^2$ and the power consumption is about 119mW/ch.

• Transactions of the Korean Society of Automotive Engineers
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• v.6 no.3
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• pp.161-168
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• 1998

This paper presents the on-vehicle information system that displays the states of the vehicle in brief words instead of symbols. Main functions of this system include a system check function, trip function, warning function, and clock function. With this system, a driver can obtain all sorts of useful information related to various conditions of the vehicle, and if any problem arises in the vehicle, he can recognize it by the displayed words with a warning sound. Also, this system is very helpful for safety driving because it displays whatever a driver wants to have concerning trip information. By experimental test and driving test, the development system shows good results for each function.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.653-654
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• 2006

A Pre-emphasis transmitter for DRAM bus system has achieved 3.2Gbps/pin operation at 1.8V supply voltage with 0.18um CMOS process. The transmitter has 800MHz PLL to generate 4 phase clocks. The 4 phase clocks are used for input clock of PRBS and multiplexing. One tap pre-emphasis is used to reduce inter symbol interference (ISI) caused by channel low pass effects. The analog calibration makes the optimized driver impedance independent with the PVT variation.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.673-675
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• 2004

This study proposes controller with voltage-compensated drivers for producing gray-scaled pictures on passive matrix organic light emitting diodes (PMOLEDs) panels. The controller includes voltage type drivers so the output impedance of the driver is far less than that of the current-type driver. Its low output impedance provides better electron-optical properties than those of traditional current drivers. A free running clock and a group of counters are applied to the gray-scaled function so that phase lock loop (PLL) circuit can be reduced in the controller. A pre-charge function is used to enhance performance of the luminance of an active OLED pixel. As a result, distribution of the low gray level portion is achieved linear relationship with input data. In this work, the digital part of the proposed controller is implemented using FPGA chips, and analog parts are combined with a digital-analog converter (DAC) and analog switches. A still image is displayed on a $48^{\ast}64$ PMOLEDs panel to assess the luminance performance fir the controller. Based on its cost requirement and luminance performance, the controller is qualified to join the market for driving PMOLEDs panels.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.776-780
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• 2007

In this paper, the charge pump circuit of a VPP generator for a low voltage DRAM is newly proposed. The proposed charge pump is a 2-stage cross coupled charge pump circuit. The charge transfer efficiency is improved, and Distributed Clock Inverter is located in each charge pump stage to reduce clock period so that the pumping current is increased. In addition, the precharge circuit is located at Gate node of charge transfer transistor to solve the problem which is that the Gate node is maintained high voltage because the boosted charge can't discharge, so device reliability is decreased. The simulation result is that pumping current, pumping efficiency and power efficiency is improved. The layout of the proposed VPP generator is designed using $0.18{\mu}m$ Triple-Well process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.71-79
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• 2010

This paper presents a design of a LLC resonant controller IC. LLC resonant controller IC controls the voltage of the 2nd side by adjusting frequency the input frequency of the external resonant circuit. The clock generator is integrated to provide the pulse to the resonant circuit and its frequency is controlled by the external resistor. Also, the frequency of the VCO is adjusted by the feedback voltage. The protection circuits such as UVLO(Under Voltage Lock Out), brown out, fault detector are implemented for the reliable and stable operation. The HVG, and LVG drivers can provide the high current and voltage to the IGBT. The designed LLC resonant controller IC is fabricated with the 0.35 um 2P3M BCD process. The overall die size is $1400um{\times}1450um$, and supply voltage is 5V, 15V.

• Journal of IKEEE
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• v.22 no.3
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• pp.742-746
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• 2018

In this paper, we implemented a VLC(Visible Light Communication) system capable of transmitting/receiving data on a 30MHz clock based on On/Off keying modulation/demodulation. The data rate of the implemented system can be verified by functional verification of VLC channel composed of LED/photodiode driver and VLC transmitting/receiving signal of Tx/Rx platform. But, In the experimental results with the VLC transmitting/receiving for combined module, the maximum transmission rate was measured at 15 MHz. Therefore, we describe the problems that can occur when implement the VLC system using the LED module with output power of 15W or more and propose ways to improve it.