• Journal of Korea Society of Industrial Information Systems
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• v.7 no.3
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• pp.1-8
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• 2002

Modular Multiplication in Galois Field GF(2/sup m/) is a basic operation for many applications, particularly for public key cryptography. This paper presents a new architecture that can process modular multiplication on GF(2/sup m/) per m clock cycles using a cellular automata. Proposed architecture is more efficient in terms of the space and time than that of systolic array. Furthermore it can be efficiently used for the hardware design for exponentiation computation.

• Journal of Computing Science and Engineering
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• v.8 no.1
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• pp.34-42
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• 2014

Time-predictability of computing is critical for hard real-time and safety-critical systems. However, currently there is no metric available to quantitatively evaluate time-predictability, a feature crucial to the design of time-predictable processors. This paper first proposes the concept of architectural time-predictability, which separates the time variation due to hardware architectural/microarchitectural design from that due to software. We then propose the standard deviation of clock cycles per instruction (CPI), a new metric, to measure architectural time-predictability. Our experiments confirm that the standard deviation of CPI is an effective metric to evaluate and compare architectural time-predictability for different processors.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.526-529
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• 2003

This paper presents two strategies to refute clock cycles when using stopping rule in VHDL model verification. The first method is that a semi-random variable is defined and the data that stay in the range of semi-random variable are skipped when stopping rule is running. The second one is to keep the old values of parameters when phases are changed. 12 VHDL models are examined to observe the effectiveness of strategies.

• The Transactions of the Korea Information Processing Society
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• v.7 no.6
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• pp.1941-1948
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• 2000

Multistage interconnection networks (MINs) have been recognized as an efficient interconnection network for high-performance computer systems and also have been recently identified to be effective for a switching fabric of new communication structures - gigabit ethernet switch, terabit router, and ATM (asynchronous transfer mode). While lots of models analyzing the performance of MINs have been proposed, they are either inaccurate or, even if accurate, very complex for the analysis. In this paper, we propose an extremely simple mode for evaluating the multibuffered MIN with small clock cycles based on the approximation approach. Comprehensive computer simulation shows that the proposed model is very accurate in terms of the throughput and mean delay. Furthermore, it significantly reduces the computing overhead due to its simplicity.

• Journal of the Korean Institute of Landscape Architecture
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• v.22 no.3
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• pp.163-174
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• 1994

In November of 1994, The Seoul Metropolitan Government celebrates its sixth centennial anniversary of becoming the capital city of Korea. In celebration of this anniversary, the Government decided to construct a plaza and sought design proposals in March of 1994. The authors collaborated on a design for the Time Capsule Plaza Competition and won fourth place among twenty-six entries. In the authors' design, the traditional oriental concept of time resonates within the site through the shape of a clock, a unique planting style, and an "Ancestral Tomb" which has a time capsule inside. The plaza is meant to be a symbol of the passage of time, the cycles of nature, and the repetitive actions of man. As for the spatial composition of the plaza, in accordance with the traditional Korean way of spatial arrangement, the plaza is divided into three parts: entry, primary, and secondary spaces. In reality, the plaza is created with the primary goal of providing modern outdoor space for people to rest and gather through the creation of pleasant environments and the introduction of traditional Korean garden elements.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1880-1885
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• 1989

In this paper, a new approach for systolic array realizing the discrete cosine transform (DCT) based on discrete Fourier transform (DFT) of an input sequence is presented. The proposed array is based on a simple modified DFT(MDFT) version of the Goertzel algorithm combined with Kung's approach and is proved perfectly. This array requires N cells, one multiplier and takes N clock cycles to produce a complete N-point DCT and also is able to process a continuous stream of data sequences. We have analyzed the output signal-to-noise ratio(SNR) and designed the circuit level layout of one-PE chip. The array coefficients are static adn thus stored-product ROM's can be used in place of multipliers to limit cost as eliminate errors due to coefficients quantization.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.118-125
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• 2016

This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.10
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• pp.132-140
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• 1997

This paper proposes systolic array architectures for compuataion of the 1-D and 2-D discrete wavelet transform (DWT). The proposed systolic array for compuataion of the 1-D DWT consists of L processing element (PE) arrays, where the PE array denotes the systolic array for computation of the one level DWT. The proposed PE array computes only the product terms that are required for further computation and the outputs of low and high frequency filters are computed in alternate clock cycles. Therefore, the proposed architecuter can compute the low and high frequency outputs using a single architecture. The proposed systolic array for computation of the 2-D DWT consists of two systolic array architectures for comutation of the 1-D DWT and memory unit. The required time and hardware cost of the proposed systolic arrays are comparable to those of the conventional architectures. However, the conventional architectures need extra processing units whereas the proposed architectures fo not. The proposed architectures can be applied to subband decomposition by simply changing the filter coefficients.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.105-108
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• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• Journal of Electrical Engineering and Technology
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• v.6 no.3
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• pp.418-422
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• 2011

For low-power sensor networks, a compact design of advanced encryption standard (AES) algorithm is needed. A very small AES core for ZigBee devices that accelerates computation in AES algorithms is proposed in this paper. The proposed AES core requires only one S-Box, which plays a major role in the optimization. It consumes less power than other block-wide and folded architectures because it uses fewer logic gates. The results show that the proposed design significantly decreases power dissipation; however, the resulting increased clock cycles for 128-bit block data processing are reasonable for IEEE 802.15.4 standard throughputs.