1 |
A. Dandalis, et al.: ‘A Comparative Study of Performance of AES Final Candidates Using FPGAs’, Lecture Notes in Computer Science, 2000, 1965, p. 133-153
|
2 |
P. Chodowiec, et al., “Very compact FPGA implementation of the AES algorithm,” Lecture Notes in Computer Science, 2003, 2779, p. 319-333
DOI
ScienceOn
|
3 |
M. Feldhofer, et al., “AES implementation on a grain of sand,” IEE Proc. Inf. Secur., 2005, 152, (1), p. 13-20
DOI
|
4 |
P. Hämäläinen, et al., “Design and implementation of low-area and low-power AES encryption hardware core,” 9th Euromicro Conf. on Digital System Design, 2006, p. 577-583
|
5 |
Wireless Medium Access Control and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LRWPAN), IEEE Std. 802.15.4, 2006.
|
6 |
Altera website, http://www.altera.com, 2008.
|
7 |
S.J. Park, “Analysis of AES Hardware Implementations”, Department of Electrical and Computer Engineering, Oregon State University, 2003
|
8 |
A. Satoh, et al., “A Compact Rijndael Hardware Architecture with S-Box Optimization”, Theory and Application of Cryptology and Information Security (ASIACRYPT 2001), Gold Coast, Australia, 2001
|
9 |
S. Morioka, et al., “An Optimized S-Box Circuit Architecture for Low Power AES Design”, Cryptographic Hardware and Embedded Systems (CHES 2002), San Francisco Bay, CA, 2002.
|
10 |
Advanced Encryption Standard (AES), FIPS Std. 197, 2001.
|
11 |
Y. Xiao, et al., “MAC Security and Security Overhead Analysis in the IEEE 802.15.4 Wireless Sensor Networks,” EURASIP Journal on Wireless Communications and Networking, 2006, p. 1-12
|