• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.7-13
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• 2010

A compact phase interpolator (PI) based spread spectrum clock generator (SSCG) for electromagnetic interference (EMI) reduction is presented. The proposed SSCG utilizes a digitally controlled phase interpolation technique to achieve triangular frequency modulation with less design complexity and small power and area overhead. The novel SSCG can generate the system clock with a programmable center-spread spectrum range of up to +/- 2 % at 200 MHz, while maintaining the clock duty cycle ratio without distortions. The PI-based SSCG has been designed and evaluated in 0.18-um 1.8-V CMOS technology, which consumes about 5.0 mW at 200MHz and occupies a chip size of $0.092mm^2$ including a DLL.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.142-147
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• 2012

This paper presents a mixed-mode CMOS duty-cycle corrector (DCC) circuit that has a dynamic frequency scaling (DFS) counter and coarse and fine tuning adjustments. A higher duty-cycle correction accuracy and smaller jitter have been achieved by utilizing the DFS counter that reduces the bit-switching glitch effect of a digital to analog converter (DAC). The proposed circuit has been designed using a 0.18-${\mu}m$ CMOS process. The measured duty cycle error is less than ${\pm}1.1%$ for a wide input duty-cycle range of 25-75% over a wide freqeuncy range of 0.5-1.5 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.168-176
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• 2015

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS'89 benchmark circuits show that our method is more accurate and efficient than previous methods.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.605-606
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• 2006

Voltage Controlled Oscillator(VCO) plays an important role in today's communication systems. Especially, a Clock Generator(CG) in phase-locked loop(PLL) is usually realized by the VCO. This paper proposes a new VCO with a controllable duty cycle buffer, that can be adopted in low-power high-speed communication systems. Delay cell of the VCO is implemented with gilbert cell. Frequency dynamic range of the VCO is in the range of approximately $50MHz{\sim}500MHz$. Parameters with N-well CMOS 0.18-um process with 1.8V supply voltage was used for the simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1160-1164
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• 1998

In this paper, we propose a new algorithm for computing multiplicative inverses in $GF(2^{m})$ and design an inversion circuit and a division circuit using this algorithm. The algorithm used is based on Fermat's theorem. It takes around m/2 clock cycles. The hardware requirements of the inversion circuit and the division circuit using this algorithm are the same as traditional circuits except for the addition of multiplexers.

• Journal of Internet Computing and Services
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• v.6 no.4
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• pp.141-147
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• 2005

Ding and Bhuyan, however, has shown that the performance of multistage interconnection networks(MIN's) can be significantly improved if the packet movements are confined within each pair of adjacent stages using small clock cycles. In this paper, an effective model for estimating the performance of multibuffered MIN's employing the approach is proposed. the relative effectiveness of the proposed model is identified compared to the traditional design.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.349-352
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• 2000

In this paper, a SIMD 64bit MAC (Multiply -Accumulate) unit is designed. It is composed of two 32bit MAC unit which supports SIMD 16bit operations. As a result, It can process two 32bit MAC operations or four 16bit operations in one cycle. Proposed MAC unit is described in Verilog HDL. After functional verification is performed, MAC unit is synthesized and optimized with 0.35$\mu\textrm{m}$ standard cell library. The synthesis result shows that this MAC unit can operate at 80㎒ of clock frequency in 85$^{\circ}C$, 3.0V, worst case process and 125㎒ of clock frequency at 25$^{\circ}C$, 3.3V, typical case process. It achieves 320Mops of performance, and is suitable for embedded DSP processors.

• Molecules and Cells
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• v.24 no.1
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• pp.37-44
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• 2007

Three catalase cDNA clones were isolated from the small radish (Raphanus sativus L.). Their nucleotide and deduced amino acid sequences showed the greatest homology to those of Arabidopsis. Genomic Southern blot analysis, using RsCat1 cDNA as a probe, showed that catalases are encoded by small multigene family in the small radish. Nondenaturing polyacrylamide gels revealed the presence of several catalase isozymes, the levels of which varied among the organs examined. The isozyme activities were assigned the individual catalase genes by Northern analysis using total RNA from different organs. The three catalase genes were differentially expressed in response to treatments such as white light, xenobiotics, osmoticum, and UV. Their expression in seedlings was controlled by the circadian clock under a light/dark cycle and/or in constant light. Interestingly, RsCat1 transcripts peaked in the morning, while those of RsCat2 and RsCat3 peaked in the early evening. Our results suggest that the RsCat enzymes are involved in defense against the oxidative stress induced by environmental changes.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.381-384
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• 1999

In this paper, we addressed the problem of reducing the switching activity in pipeline datapath and proposed a solution. clock-gating method is a kind of practical technique for reducing switching activity in finite state machine. But, in the case that the target gated function unit has a pipeline structure, there is some spurious switching activity on each stage register group. This occur in early stage of every function enable cycle. In this paper we proposed a method to solve this problem. This method generates the enable signal to each pipeline stage to gate the clock feeding register group. Experimental results showed effective reduction of dynamic powers in pipeline circuits.