• Journal of Electrical Engineering and Technology
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• v.7 no.3
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• pp.429-435
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• 2012

In this study, a real-time architecture for the detection of clock jumps in the GPS clock behavior is proposed. GPS satellite atomic clocks have characteristics of a second order polynomial in the long term showing sudden jumps occasionally. As satellite clock anomalies influence on GPS measurements which could deliver wrong position information to users as a result, it is required to develop a real time technique for the detection of the clock anomalies especially on the real-time GPS applications such as aviation. The proposed strategy is based on Teager Energy operator, which can be immediately detect any changes in the satellite clock bias estimated from GPS carrier phase measurements. The verification results under numerous cases in the presence of clock jumps are demonstrated.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.191-196
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• 2005

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver has been designed and implemented. It consists of a clock recovery circuit, a RF mixer and frequency discriminator for phase/frequency detection, a DR-VCO, a phase shifter, and a hold circuit. The recovered 40 GHz clock is synchronized with a stable 10 GHz DR-VCO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module has shown to significantly improve the performance of the conventional open-loop type clock recovery module with DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When input signal is dropped, the 40 GHz clock is generated continuously by hold circuit. The implemented clock recovery module can be used as a low-cost and high-performance receiver module for 40 Gb/s commercial optical network.

• Earthquakes and Structures
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• v.22 no.1
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• pp.65-82
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• 2022

This paper presents a structural performance assessment of a historical masonry clock tower both using numerical and experimental process. The numerical assessment includes developing of finite element model with considering different types of soil-structure interaction systems, identifying the numerical dynamic characteristics, finite element model updating procedure, nonlinear time-history analysis and evaluation of seismic performance level. The experimental study involves determining experimental dynamic characteristics using operational modal analysis test method. Through the numerical and experimental processes, the current structural behavior of the masonry clock tower was evaluated. The first five experimental natural frequencies were obtained within 1.479-9.991 Hz. Maximum difference between numerical and experimental natural frequencies, obtained as 20.26%, was reduced to 4.90% by means of the use of updating procedure. According to the results of the nonlinear time-history analysis, maximum displacement was calculated as 0.213 m. The maximum and minimum principal stresses were calculated as 0.20 MPa and 1.40 MPa. In terms of displacement control, the clock tower showed only controlled damage level during the applied earthquake record.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.28 no.6
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• pp.563-571
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• 2010

The GPS satellite has three or four atomic clocks that consist of cesiums and rubidiums and the NANU messages can be used to identify the kind of the onboard atomic clock because they classify the clock type on a daily basis. In this study, for long-term analysis of the GPS satellite clock behavior, we extracted satellite clock errors for every PRN from years 2001 through 2009 using the SP3 files that are provided by the IGS. As a result, the cesium clock offsets usually have a linear trend of drifting. On the other hand, rubidium offsets show curvilinear variations in general, even though they cannot be represented as anyone specific polynomial function. For short-term analysis, we extracted satellite clock errors for each PRN for a week-long period using the CLK files that are also provided by the IGS and curve-fitted them with first-order and second-order polynomial functions. In cases of cesium clock errors, they were well-represented by first-order polynomial functions and rubidium clock errors were similar with second-order polynomials. However, some of rubidium clock errors could not be represented as any polynomial fitting function. To analyze the characteristic of GPS satellite by each block and atomic clock, we applied Modified Allan Deviation criterion to the dataset from years 2007 and 2010. We found that the Modified Allan Deviation characteristics changed significantly according the block and atomic clock type.

• Journal of the Korea Society of Computer and Information
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• v.24 no.7
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• pp.1-8
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• 2019

Recently, an SSD with hybrid buffer memories is actively researching to reduce the overall latency in server computing systems. However, existing hybrid buffer policies caused many swapping operations in pages because it did not consider the overall latency such as read/write operations of flash chips in the SSD. This paper proposes the clock with hybrid buffer memories (CLOCK-HBM) for a new hybrid buffer policy in the SSD with server computing systems. The CLOCK-HBM constructs new policies based on unique characteristics in both DRAM buffer and NVMs buffer for reducing the number of swapping operations in the SSD. In experimental results, the CLOCK-HBM reduced the number of swapping operations in the SSD by 43.5% on average, compared with LRU, CLOCK, and CLOCK-DNV.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.2062-2073
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• 1997

The important articles we must consider in SDH network and system design are the number of maximum nodes and clock characteristics of each node. In order to get these, the study of characteristics about some clock states, such as normal state and phase transient state, on the standard specifications is required. In this paper, we presented MTIE and TDEV characteristics with ITU-T & ANSI standard specifications in some clock states of the SDH linear networks, and proposed the number of maximum nodes satisfying above two standards. Also our resulsts are compared with AT&T's.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.123-134
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• 2004

The synchronized clock performance in the synchronization network and SDH transmission network design is an important element in aspect of guaranteeing network stability and data transmission. Consequently the simulator which can applicable various parameters and several input levels from the best state to the worst state for performance analysis of the synchronized clock is required in case of network design. Therefore, in this paper, 1 developed the SNCA and TNCA for analysis of the synchronized clock in the synchronization network and transmission network. And utilizing these simulators with various wander generation, node number and clock state, 1 obtained the synchronized clock characteristics and maximum network nodes In NE1, NE2 and NE3 transmission network and DOTS1, DOTS2 synchronization network.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.171-177
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• 2006

A low-cost, high-performance 40 Gb/s clock recovery module using a phase-locked loop(PLL) for a 40 Gb/s optical receiver with the clock-hold function has been designed and implemented. It consists of a clock extractor circuit, an RF mixer and a frequency discriminator for phase/frequency detection, a VC-DRO, a phase shifter, and a clock-hold circuit. The extracted 40 GHz clock is synchronized with a stable 10 GHz VC-DRO. The clock stability and jitter characteristics of the implemented PLL-based clock recovery module are significantly improved as compared with those of the conventional open-loop type clock recovery module with a DR filter. The measured peak-to-peak RMS jitter is about 230 fs. When an input signal is dropped, the 40 GHz clock is maintained continuously by the hold circuit.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.36 no.6
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• pp.621-628
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• 2018

More than four visible GPS (Global Positioning System) satellites are required to obtain absolute positioning. However, it is not easy to satisfy this condition when a rover is in such unfavorable condition as an urban area. As a consequence, clock-aided positioning has been used as an alternative method especially when the number of visible satellites is three providing that receive clock error information is available. In this study, LSC (Least-Squares Collocation) method is proposed to interpolate clock errors for clock-aided positioning after analyzing the characteristics of receiver clock errors. Numerical tests are performed by using GPS data collected at one of Korean CORS (Continuously Operating Reference Station) and a nearby GPS station. The receiver clock errors are obtained through the DGPS (Differential GPS) positioning technique and segmentation procedures are applied for efficient interpolation. Then, LSC is applied to predicted clock error at epoch which clock information is not available. The numerical test results are analyzed by examining the differences between the original and interpolated clock errors. The mean and standard deviation of the residuals are 0.24m and 0.49m, respectively. Therefore, it can be concluded that sufficient accuracy can be obtained by using the proposed method in this study.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6B
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• pp.305-315
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• 2007

In this paper, We generated a wander generation model from really measured clock noise data on the transmission node and DOTS in NG-SDH network. and then, We presented the performance of Synch. clock and maximum node level capable network configuration through the clock characteristics simulation on network having the steady-state clock.