• 정보처리학회논문지A
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• 제9A권1호
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• pp.61-74
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• 2002

본 논문에서는 시간 제한 조건을 가진 자유 선택 신호 전이 그래프로부터 비동기 회로를 합성하는 방법을 기술한다. 이 방법에서는 상태 그래프를 생성하지 않고 신호 전이 그래프로부터 직접 신호 전이들간의 관계를 구하여 비동기 회로를 합성한다. 본 논문의 합성 방법에서는 자유 선택 신호 전이 그래프를 선택 행위가 없는 결정성 신호 전이 그래프에 대하여 타이밍 분석을 수행하여 임의의 두 신호 전이 사이의 시간 제약 병렬 관계와 시간 제약 인과 관계를 구한다. 다음에는 이 관계들을 이용하여 각 결정성 신호 전이 그래프에 대한 합성을 수행하고 그 결과를 합병함으로써 전체 회로를 합성한다. 실험 결과에 의하면 본 논문에서 제안한 합성 방법은 상태 공간이 큰 회로에 대하여 현저하게 합성시간을 단축시킬 수 있을 뿐 만 아니라 기존의 상태 그래프 기반 합성 방법과 비교하여 거의 같은 면적의 회로를 합성한다.

• 제어로봇시스템학회논문지
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• 제9권11호
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• pp.952-957
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• 2003

We propose how to translate relay circuits to the EMFGs(Extended Mark Flow Graphs) formally and analyze the original one by using the mark flow of it. Firstly, the concepts of the output condition, the output-on condition and the output-off condition are introduced in the relay circuits. These can be used to find the structure and the operation of respective relay outputs but the sequential operations of them cannot be obtained from these. Secondly, a relay circuit is translated to the corresponding EMFG as the all output-on conditions and all output-off conditions of it are translated to EMFGs. For the adequate translation, the condition arc and the concepts of the generation transition and the degeneration transition are introduced, and the duality for the simplification of the result. Thirdly, we analyze the operation of the original circuit by analyzing the mark flow of the resulting EMFG. We can achieve easy and fast analysis based on the EMFG's operation algorithm. Finally, we apply these to the relay circuit for an electric furnace and analyze its operation with the mark flow of the resulting EMFG. The formal translation from relay circuits to EMFGs makes the analysis easy so that these results can be used to design, modelling, the fault detection and the maintenance.

• 대한전자공학회논문지
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• 제11권4호
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• pp.17-22
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• 1974

본논문에서는 조합논리회로의 결함검출에 관한 문제를 취급하였는데 먼저 fan-out가 없는 회로에 대한 결함검출방법을 논하고 이 방법을 fan-out가 있는 회로에 확장하였다. Fan-out가 있는 회로에서는 내부 fan-out점을 전후하여 fan-out가 없는 부분회로로 분리구분하고 우선 각 부분회로에 대한 최소테스트집합을 구한다. 다음에 각 부분테스트집합사이에서 최대한으로 병립가능한 테스트를 조합하여 전체회로에 대한 종합적인 입력테스트벡터를 구한다. 이와같은 절차에 의하면 테스트수가 최소인 완전테스트집합이 용이하게 구해질 뿐만 아니라 검출가능한 결함 및 불가능한 결함이 명확하게 판가름 된다.

• Journal of electromagnetic engineering and science
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• 제13권1호
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• pp.54-61
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• 2013

An equivalent model has been developed to estimate the electromagnetic immunity for integrated circuits under a complex electromagnetic environment. The complete model is based on the characteristics of the equipment and physical configuration of the device under test (DUT) and describes the measurement setup as well as the target integrated circuits under test, the corresponding package, and a specially designed printed circuit board. The advantage of the proposed model is that it can be applied to a SPICE-like simulator and the immunity of the integrated circuits can be easily achieved without costly and time-consuming measurements. After simulation, measurements were performed to verify the accuracy of the equivalent model for immunity prediction. The improvement of measurement accuracy due to the added effect of a bi-directional coupler in the test setup is also addressed.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1999년도 전력전자학술대회 논문집
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• pp.266-269
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• 1999

Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both voltage-fed and current-fed electronic ballast. The proposed PFC circuits use valley-fill(VF) type DC-link stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant capacitors. In current-fed type, the charge pump capacitors are connected with the additional secondary-side of the power transformer. The measured PF and THD are higher than 0.99 and 15% for all proposed PFC circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• 대한전자공학회논문지SD
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• 제37권11호
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• pp.105-114
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• 2000

지연 고장을 위한 테스트는 디지털 회로의 속도와 직접도가 크게 향상되면서 필수적인 것으로 생각되고 있다. 그러나, 순차 회로에는 상태 레지스터들이 있기 때문에, 지연 고장을 검출하는 것이 쉽지 않다. 이러한 난점을 해결하기 위해 회로의 단일 고착 고장과 지연 고장을 효율적으로 검출할 수 있는 새로운 테스트 방법과 알고리듬을 개발하였고 이를 적용하기 위한 새로운 구조의 스캔 플립-플롭을 제안한다. ISCAS 89 벤치마크 회로에 대한 실험을 통해 지연 고장 검출률이 기존의 전통적인 스캔 테스트 방법에 비해 현격하게 향상된 것을 알 수 있다.

• 대한전자공학회논문지
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• 제13권4호
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• pp.12-17
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• 1976

구논문은 ULM(Universal Logic Modules)의 구성과 특징에 관하여 고찰하고 TULM, QULM 및 SULM에 관하여 분석하였으며 대칭함수를 도입하여 ULM 회로의 간소화를 시도하였다. 대칭함수에 의한 간소화결과를 ULM으로 실현시키기 위하여 54/74류 집적회로를 써서 10KHz의 발진회로를 구성하여 이론적 결과와 대응함을 관찰하였다. This paper deals with characteristics and analysis of the Universal Logic Modules as well as TULM, QULM and SULM. Studies are made on minimization in Storms of symmetric circuits and theoretical stuides are made by using the symmetric functions The symmetric circuits of the ULM are realized by employing 54/74 ICs, An oscillator circuit of 10KHz. is constructed based on the ULM. The experimental results gave a good agreement with the theoretical Minimization.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.267-273
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• 2007

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in $0.18-{\mu}m$ CMOS, the PLL covers $154{\sim}303$ MHz (VHF-III), $462{\sim}911$ MHz (UHF), and $1441{\sim}1887$ MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

• Journal of Power Electronics
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• 제16권5호
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• pp.1661-1668
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• 2016

A fixed off-time controlled high power factor ac-dc LED driver is proposed in this paper, which employs a novel zero-crossing-compensation (ZCC) circuit based on a fixed off-time controlled scheme. Due to the parasitic parameters of the system, the practical waveforms have a dead region. By detecting the zero-crossing boundary, the proposed ZCC circuit compensates the control signal VCOMP within the dead region, and is invalid above this region. With further optimization of the parameters KR and Kτ of the ZCC circuit, the dead zone can be eliminated and lower THD is achieved. Finally, the chip is implemented in HHNEC 0.5μm 5V/40V HVCMOS process, and a prototype circuit, delivering 7~12W of power to several 3-W LED loads, is tested under AC input voltage ranging from 85V to 265V. The test results indicate that the average total harmonic distortion (THD) of the entire system is approximately 10%, with a minimum of 5.5%, and that the power factor is above 0.955, with a maximum of 0.999.

• Journal of Communications and Networks
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• 제9권1호
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• pp.93-104
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• 2007

Traffic grooming, in which low-rate circuits are multiplexed onto wavelengths, with the goal of minimizing the number of add-drop multiplexers (ADMs) and wavelengths has received much research attention from the optical networking community in recent years. While previous work has considered various traffic models and network architectures, protection requirements of the circuits have not been considered. In this paper, we consider survivable traffic grooming, or grooming traffic which contains a mix of circuits that need protection and that do not need protection. We assume a unidirectional ring network with all-to-all symmetric traffic with $t\geq1$ circuits between each node pair, of which s require protection. As it turns out, survivable traffic grooming presents a significant tradeoff between the number of wavelengths and the number of ADMs, which is almost non-existent in non-survivable traffic grooming for this type of traffic. We explore this tradeoff for some specific cases in this paper. We also present some new results and solution methods for solving certain non-survivable traffic grooming problems.