• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.423-429
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• 2013

A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.

• 전자공학회논문지B
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• 제31B권4호
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• pp.55-61
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• 1994

The multiple valued logic(MVL) circuit with ROM type using current mode CMOS is presented in this paper. This circuit is composed of the multiple valued-to-binary(MV/B) decoder and the selection circuit. The MV/B decoder decodes the single input multiple valued signal to N binary signal, and the selection circuits is composed N$\times$N array of the selecion cells with ROM types. The selection cell is realized with the current mirror circuits and the inhibit circuits. The presented circuit is suitable for designing the circuit of MVL functions with independent variables, and reduces the number of selection cells for designing the circuit of symmetric MVL functions as many as {($N^2$-N)/2}+N. This circuit possess features of simplicity. expansibility for array and regularity, modularity for the wire routing. Also, it is suitable for VLSI implementation.

• 전자공학회논문지C
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• 제35C권7호
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• pp.46-58
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• 1998

In this paper, we propose a synthesis algorithm for the design of low powe rcombinational circuits under area constraints. The proposed algorithm partitions a given circuit into several subcircuits such that only a selected subcircuit is activated at a time, hence reduce unnecessary signal transitions. Partitioning of a given circuit is performed through adaptive simulated annealing algorithm employing the cost function reflecting poer consumption under area constraints. Experimental reuslts for the MCNC benchmark circuits show that the proposed algorithm generates the circuits which consume less power by 61.1% and 51.1%, when compared to those generated by the sis 1.2 and the precomputation algorithm, respectively.

• 전자공학회논문지A
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• 제31A권2호
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• pp.94-103
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• 1994

In testing for practical scan disigned logic circuits, there may exist logic value constraints on some part of primary inputs due to various requirements on design and test. This paper presents a logic value system called taboo logic values which targets the test pattern generation of logic circuits under logic value constraints. The taboo logic system represents the logic value constraints and identifies additional logic value constraints through the implication of the tqaboo logic values using a taboo logic calculus. Those identified logic value constraints will guide the search during the test pattern generation of avoid the unfruitful searches and to identify redundant faults due to the logic value constraints very quickly. Finally, experimental results on ISCAS85 benchmark circuits will demonstrate the efficiency of the taboo logic values.

• Journal of Korean Vacuum Science & Technology
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• 제3권1호
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• pp.66-73
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• 1999

In this paper, the design of one-chip FED system integrated with driving circuits in reported on the basis of MOSFET controlled FEA (MCFEA). To integrate a MOSFET with a FEA efficiently, a new fabrication process is proposed. It is confirmed that the MOSFET with threshold voltage of about 2volts controls the FEA emission current up to 20 ${\mu}$A by applying driving voltage of 15 volts, which is enough current level to utilize the MCFEA as a pixel for FED. The drain breakdown voltage of the MOSFET is measured to be 70 volts, which is also high enough for 60 volt operation of FED. The circuits for row and column driver are designed stressing on saving area, reducing malfunction probability and consuming low power to maximize the merit of on-chip driving circuits. Dynamic logic concept and bootstrap capacitors are used to meet these requirements. By integrating the driving circuit with FEA, the number of external I/O lines can be less than 20, irrespectively of the number of pixels.

• Molecules and Cells
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• 제39권9호
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• pp.645-653
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• 2016

Morphine is the most potent analgesic for chronic pain, but its clinical use has been limited by the opiate's innate tendency to produce tolerance, severe withdrawal symptoms and rewarding properties with a high risk of relapse. To understand the addictive properties of morphine, past studies have focused on relevant molecular and cellular changes in the brain, highlighting the functional roles of reward-related brain regions. Given the accumulated findings, a recent, emerging trend in morphine research is that of examining the dynamics of neuronal interactions in brain reward circuits under the influence of morphine action. In this review, we highlight recent findings on the roles of several reward circuits involved in morphine addiction based on pharmacological, molecular and physiological evidences.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.534-536
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• 2009

We have fabricated solution-processed zinc-tin oxide thin film transistors (TFTs) and simple circuits on glass substrates. We report a solutionprocessed zinc-tin oxide TFTs on silicon wafer with mobility greater than 9 $cm^2/V{\cdot}s$ (W/L = 100/5 ${\mu}m$) and threshold voltage variation of less than 1 V after bias-stressing. Also, we fabricated solution-processed zinc-tin oxide circuits including inverters and 7-stage ring oscillators fabricated on glass substrates using the developed zinc-tin oxide TFTs.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.109-112
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• 2003

Small impedances in the superconducting parallel circuits cause unequal distribution of the currents in the circuits. This results in quenches or losses in some superconducting parts and decrease of total transport current. This paper presents the fabrication and test results of a superconducting multi- interphase transformers (SIPT) for equal current distribution in superconducting parallel circuits. The secondary loop configuration with air core SIPT seems to be the most efficient one for the SFCL. Test results show that the SIPT can effectively make the current distribution uniform in Parallel circuits that have unequal resistances.

• ETRI Journal
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• 제31권2호
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• pp.209-214
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• 2009

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece-wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.1119-1122
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• 2000

This paper describes on RF circuit simulation technique, especially on a RF modeling and a model extraction of a LDMOS(Lateral Diffused MOS) that has gate-width (Wg) dependence. Small-signal model parameters of the LDMOSs with various gate-widths extracted from S-parameter data are applied to make the relation between the RF performances and gate-width. It is proved that a source inductance (Ls) was not applicable to scaling rules. These extracted small-signal model parameters are also utilized to remove extrinsic elements in an extraction of a large-signal model (using HP Root MOSFET Model). Therefore, we can omit an additional measurement to extract extrinsic elements. When the large-signal model with Ls having the above gate-width dependence is applied to a high-power LDMOS module, the simulated performances (Output power, etc.) are in a good agreement with experimental results. It is proved that our extracted model and RF circuit simulation have a good accuracy.