• Journal of the Korean Institute of Intelligent Systems
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• v.16 no.5
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• pp.627-634
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• 2006

We have proposed the methods how to control the slope of CMOS inverter's characteristic and how to shift it in y axis. We control the MOS transistor threshold voltage for these methods. By observing that two transistors are in saturation region at the center of the CMOS inverter's characteristic, we have presented how to make the characteristic for one pole neuron. The circuit level simulation is used for verifying the proposed method. PSpice(OrCAD Co.) is used for circuit level simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.28-33
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• 2013

Spin-torque oscillators (STO) is a new device that can be used as a tunable microwave source in various wireless devices. Spin-transfer torque effect in magnetic multilayered nanostructure can induce precession of magnetization when bias current and external magnetic field are properly applied, and a microwave signal is generated from that precession. We proposed a semi-empirical circuit-level model of an STO in previous work. In this paper, we present a refined STO model which gives more accuracy by considering physical phenomena in the calculation of effective field. Characteristics of the STO are expressed as functions of external magnetic field and bias current in Verilog-A HDL such that they can be simulated with circuit-level simulators such as Hspice. The simulation results are in good agreement with the experimental data.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1998.10a
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• pp.827-834
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• 1998

This paper describes a multi-level simulation technique and its implementation, which accurately solve voltages and currents of circuits descreibed at mixed levels of abstractions. A metho to form a tightly coupled simulation environment is proposed and, starting from a description of a circuit, simulation set-up and analysis procedure of the multi-level simulator for a transient response are presented. Circuit and behavioral simulation techniques and their implementations composing the multi-level simulation are explained in detail. Most of the algorithms implemented in the simulation are based upon the standard simulation techniques in order to obtain the reliability and accuracy of conventinoal simulators. Simulation examples show that the multi-level simulator can analyze circuits containing highly nonlinear behavioral models without loss of accuracy provided the behavioral models are accurate enough.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.146-155
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• 1994

In this paper, we desribe a new system, called BEST, that is used to develop a macromodel or behavioral model easily. It automatically calculates the component values of macromodel represented by equations to satisfy the given specification. Also, it gives the way to analyze both the behavioral model and transistor level circuit, and then compare the analysis results of them to check the correspondence under specific temperature and bias condition, and BEST optimizes the component values of macromodel. Other feature is to characterize MOSFET as switch model which consists of PWL-RC network. Finally, it is possible to generage multi-level netlist which consists of macro/switch/transistor level circuits, and user can determine the trade-off between simulation speed and accuracy. With the graphic user interface form of macromodel development system described above. BEST enable designers to make macromodel by themselves and to uas it. We applied BEST to develop the macromodel for the test circuit and got the 18.6 times simulation speed up with preserving the accuracy within 10% compared to the conventional transistor level circuit simulation. Also, applicability of optimization capability was verified.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.1
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• pp.13-17
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• 2013

In this paper, we designed a charge pump circuit using level shifter for LED driver IC. The designed circuit makes the 15 V output voltage from the 5 V input in condition of 50 kHz switching frequency. The prototype chip which include the proposed charge pump circuit and its several internal sub-blocks such as oscillator, level shifter was fabricated using a 0.35 um 20 V BCD process technology. The size of the fabricated prototype chip is 2,350 um ${\times}$ 2,350 um. We examined performances of the fabricated chip and compared its measured results with SPICE simulation data.

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.107-114
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• 1994

This paper describes an integrated environment for logic circuit simultion which is an important step of logic circuit design. The system consists of a logic simulator kernel, an expandible element routine library. a functional level element routine generator, several HDL input parsers, and a postprocessor. The system can simulate the same system in several levels of hierarchy. The experimental result shows that the system is very efficient and useful for design of logic circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.319-329
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• 2016

High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuit-level simulation using Verilog-A blocks are used to validate our approach.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.20-23
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• 2008

We proposed a-Si:H TFT (hydrogenated amorphous silicon thin film transistor) level shifter which reduced number of power sources. To reduce the number of power sources from four to two, modified bootstrapped inverter was used for the level shifter. The shift register was verified by PSPICE circuit simulation and fabricated. The fabricated level shifter successfully shifted low input (0 to 5 V) to high level output (-7 to 23 V).

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.354-357
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• 1999

This paper is proposed Single phase Multi-Level AC-DC Converter. This is consist of diode bridge and switches. The number of the supply current levels depends on the number of the individual converter's current level. In this converter circuit the number of the levels is equal to 2(M+1) -1, where M is the number of Switching-Leg's number. In this paper is introduced converter with 31 current Level. If the number of current level is increased, smoother sinusoidal waveform can be obtained. The feasibility of the circuit is verified by computer simulation using PSIM

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.93-102
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• 1994

This paper, presents SECRET(SEC REliability Tool), which predicts reliability problems related to the hot-carrier and electromigration effects on the submicron MOSFETs and interconnections. To simulate DC and AC lifetime for hot-carrier damaged devices, we have developed an accurate substrate current model with the geometric sensitivity, which has been verified over the wide ranges of transistor geometries. A guideline can be provided to design hot-carrier resistant circuits by the analysis of HOREL(HOT-carrier RFsistant Logic) effect, and circuit degradation with respect to physical parameter degradation such as the threshold voltage and the mobility can also be expected. In SECRET, DC and AC MTTF values of metal lines are calculated based on lossy transmission line analysis, and parasitic resistances, inductances and capacitances of metal lines are accurately considered when they operate in the condition of high speed. Also, circuit-level reliability simulation can be applied to the determination of metal line width and-that of optimal capacitor size in substrate bias generation circuit. Experimental results obtained from the several real circuits show that SECERT is very useful to estimate and analyze reliability problems.