• Title/Summary/Keyword: circuit power

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Design of a CMOS x-ray line scan sensors (CMOS x-ray 라인 스캔 센서 설계)

  • Heo, Chang-Won;Jang, Ji-Hye;Jin, Liyan;Heo, Sung-Kyn;Kim, Tae-Woo;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.10
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    • pp.2369-2379
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    • 2013
  • A CMOS x-ray line scan sensor which is used in both medical imaging and non-destructive diagnosis is designed. It has a pixel array of 512 columns ${\times}$ 4 rows and a built-in DC-DC converter. The pixel circuit is newly proposed to have three binning modes such as no binning, $2{\times}2$ binning, and $4{\times}4$ binning in order to select one of pixel sizes of $100{\mu}m$, $200{\mu}m$, and $400{\mu}m$. It is designed to output a fully differential image signal which is insensitive to power supply and input common mode noises. The layout size of the designed line scan sensor with a $0.18{\mu}m$ x-ray CMOS image sensor process is $51,304{\mu}m{\times}5,945{\mu}m$.

Design of a Inverter-Based 3rd Order ΔΣ Modulator Using 1.5bit Comparators (1.5비트 비교기를 이용한 인버터 기반 3차 델타-시그마 변조기)

  • Choi, Jeong Hoon;Seong, Jae Hyeon;Yoon, Kwang Sub
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.7
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    • pp.39-46
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    • 2016
  • This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.

Design of a step-up DC-DC Converter using a 0.18 um CMOS Process (0.18 um CMOS 공정을 이용한 승압형 DC-DC 컨버터 설계)

  • Lee, Ja-kyeong;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.6
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    • pp.715-720
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    • 2016
  • This paper proposes a PWM (Pulse Width Modulation) voltage mode DC-DC step-up converter for portable devices. The converter, which is operated with a 1 MHz switching frequency, is capable of reducing the mounting area of passive devices, such as inductor and capacitor, and is suitable for compact mobile products. This step-up converter consists of a power stage and a control block. The circuit elements of the power stage are an inductor, output capacitor, MOS transistors Meanwhile, control block consist of OPAMP (operational amplifier), BGR (band gap reference), soft-start, hysteresis comparator, and non-overlap driver and some protection circuits (OVP, TSD, UVLO). The hysteresis comparator and non-overlapping drivers reduce the output ripple and the effects of noise to improve safety. The proposed step-up converter was designed and verified in Magnachip/Hynix 0.18um 1-poly, 6-metal CMOS process technology. The output voltage was 5 V with a 3.3 V input voltage, output current of 100 mA, output ripple less than 1% of the output voltage, and a switching frequency of 1 MHz. These designed DC-DC step-up converters could be applied to the Personal Digital Assistants(PDA), cellular Phones, Laptop Computer, etc.

GaN HPA Monolithic Microwave Integrated Circuit for Ka band Satellite Down link Payload (Ka 대역 위성통신 하향 링크를 위한 GaN 전력증폭기 집적회로)

  • Ji, Hong-Gu
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.12
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    • pp.8643-8648
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    • 2015
  • In this paper presents the design and demonstrate 8 W 3-stage HPA(High Power Amplifier) MMIC(Monolithic Microwave Integrated Circuits) for Ka-band down link satellite communications payload system at 19.5 GHz ~ 22 GHz frequency band. The HPA MMIC consist of 3-stage GaN HEMT(Hight Electron Mobility Transistors). The gate periphery of $1^{st}$ stage, $2^{nd}$ stage and output stage is determined $8{\times}50{\times}2$ um, $8{\times}50{\times}4$ um and $8{\times}50{\times}8$ um, respectively. The fabricated HPA MMIC shows size $3,400{\times}3,200um^2$, small signal gain over 29.6 dB, input matching -8.2 dB, output matching -9.7 dB, output power 39.1 dBm and PAE 25.3 % by using 0.15 um GaN technology at 20 V supply voltage in 19.5~22 GHz frequency band. Therefore, this HPA MMIC is believed to be adaptable Ka-band satellite communication payloads down link system.

The surface kinetic properties of $ZrO_2$ Thin Films in dry etching by Inductively Coupled Plasma

  • Yang-Xue, Yang-Xue;Kim, Hwan-Jun;Kim, Dong-Pyo;Um, Doo-Seung;Woo, Jong-Chang;Kim, Chang-Il
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.105-105
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    • 2009
  • $ZrO_2$ is one of the most attractive high dielectric constant (high-k) materials. As integrated circuit device dimensions continue to be scaled down, high-k materials have been studied more to resolve the problems for replacing the EY31conventional $SiO_2$. $ZrO_2$ has many favorable properties as a high dielectric constant (k= 20~25), wide band gap (5~7 eV) as well as a close thermal expansion coefficient with Si that results in good thermal stability of the $ZrO_2/Si$ structure. In order to get fine-line patterns, plasma etching has been studied more in the fabrication of ultra large-scale integrated circuits. The relation between the etch characteristics of high-k dielectric materials and plasma properties is required to be studied more to match standard processing procedure with low damaged removal process. Due to the easy control of ion energy and flux, low ownership and simple structure of the inductively coupled plasma (ICP), we chose it for high-density plasma in our study. And the $BCl_3$ included in the gas due to the effective extraction of oxygen in the form of $BCl_xO_y$ compound In this study, the surface kinetic properties of $ZrO_2$ thin film was investigated in function of Ch addition to $BCl_3/Ar$ gas mixture ratio, RF power and DC-bias power based on substrate temperature. The figure 1 showed the etch rate of $ZrO_2$ thin film as function of gas mixing ratio of $Cl_2/BCl_3/Ar$ dependent on temperature. The chemical state of film was investigated using x-ray photoelectron spectroscopy (XPS). The characteristics of the plasma were estimated using optical emission spectroscopy (OES). Auger electron spectroscopy (AES) was used for elemental analysis of etched surface.

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A Study on the reduction of surface roughness by analyzing the thickness of photocurable sculpture (광조형물의 패턴두께에 따른 표면 거칠기 저감을 위한 공정연구)

  • Kim, Young-Su;Yang, Hyoung-Chan;Kim, Go-Beom;Dang, Hyun-Woo;Doh, Yang-Hoi;Choi, Kyung-Hyun
    • Journal of Power System Engineering
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    • v.20 no.4
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    • pp.75-82
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    • 2016
  • In this paper, we developed a 3D printing system using a photo-curing resin in order to reduce the surface roughness of a sculpture produced with the 3D printer. Using the pattern of the resulting variable thickness, that gave rise to a stepped shape, and the area error of the photo-curable sculpture, a study was carried out for the process to reduce the surface roughness. At a given value of stage velocity (40~70 mm/s) and output air pneumatic pressure (20~60 kPa), the minimum pattern thickness of the pattern was achieved $65{\mu}m$ and the maximum pattern thickness of up to $175{\mu}m$. To increases the pattern resolution to about $40{\mu}m$, the process conditions should be optimized. 3D surface Nano profiler was used to find the surface roughness of the sculpture that was measured to be minimum $4.7{\mu}m$ and maximum $8.7{\mu}m$. The maximum surface roughness was reduced about $1.2{\mu}m$ for the maximum thickness of the pattern. In addition, a FDM was used to fabricate the same sculpture and its surface roughness measurements were also taken for comparison with the one fabricated using photo-curing. Same process conditions were used for both fabrication setups in order to perform the comparison efficiently. The surface roughness of the photo-curable sculpture is $5.5{\mu}m$ lower than the sculpture fabricated using FDM. A certain circuit patterns was formed on the laminated surface of the photo-curable sculpture while there was no stable pattern on the laminated surface of the FDM based sculpture the other hand.

Identification of Motor Parameters and Improvement of Voltage Error for Improvement of Back-emf Estimation in Sensorless Control of Low Speed Operation (저속 센서리스 제어의 역기전력 추정 성능 향상을 위한 모터 파라미터 추정과 전압 오차의 개선)

  • Kim, Kyung-Hoon;Yun, Chul;Cho, Nae-Soo;Jang, Min-Ho;Kwon, Woo-Hyen
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.67 no.5
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    • pp.635-643
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    • 2018
  • This paper propose a method to identify the motor parameters and improve input voltage error which affect the low speed position error of the back-emf(back electromotive force) based sensorless algorithm and to secure the operation reliability and stability even in the case where the load fluctuation is severe and the start and low speed operation frequently occurs. In the model-based observer used in this paper, stator resistance, inductance, and input voltage are particularly influential factors on low speed performance. Stator resistance can cause resistance value fluctuation which may occur in mass production process, and fluctuation of resistance value due to heat generated during operation. The inductance is influenced by the fluctuation due to the manufacturing dispersion and at a low speed where the change of the current is severe. In order to find stator resistance and inductance which have different initial values and fluctuate during operation and have a large influence on sensorless performance at low speed, they are commonly measured through 2-point calculation method by 2-step align current injection. The effect of voltage error is minimized by offsetting the voltage error. In addition, when the command voltage is used, it is difficult to estimate the back-emf due to the relatively large distortion voltage due to the dead time and the voltage drop of the power device. In this paper, we propose a simple circuit and method to detect the voltage by measuring the PWM(Pulse Width Modulation) pulse width and compensate the voltage drop of the power device with the table, thereby minimizing the position error due to the exact estimation of the back-emf at low speed. The suitability of the proposed algorithm is verified through experiment.

Automation of Longline -Automation of the Alaska Pollack Longline- (주낙어구의 자동화 -명태주낙어업의 자동화-)

  • KO Kwan-Soh;YOON Gab-Dong;LEE Chun-Woo
    • Korean Journal of Fisheries and Aquatic Sciences
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    • v.20 no.2
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    • pp.106-113
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    • 1987
  • The Alaska pollack longline operations, which consist of baiting, shooting, hauling and arrangement of hooks, are dependant on manual labour up to the present. The automation against this traditional way is necessary to eliminate the manual operations and to reduce crew. We have developed a prototype longline system suitable for Alaska pollack longline gear, which is composed of an automatic baiting machine, an automatic line hauler, a hook cleaner and storage rails. The automatic bailing machine driven by hydraulic power is precise baiting method controlled sequentially, and the automatic line hauler is to haul up the mainline by means of hydraulic power and at the same time to split every hook and to carry it onto storage rail automatically. A series functioning tests on shooting and hauling apparatus were carried out in the laboratory and at sea. The results obtained are as follows ; 1. As for the baiting machine, the exciting time of solenoid which operates a directional valve, bait feeding and cutting time, is shortened according to the increase of pressure, and also, after cutting the bait, the over-rotated angle of the blade increased in accordance with the increase of pressure. 2. The baiting efficiency is about $90\%$ when using sand lance (Hypoptychus dybowskii), and the most proper pressure of the hydraulic circuit in feeding and cutting the bait is between $13\;kgf/cm^2\;and\;20\;kgf/cm^2$. 3. The hook splitting rate of the automatic line hauler is about $95.5\%$ regardless of hauling speed and materials of snood. 4. The case of unseparating hook is appeared when the snood gets entangled or the hook is sticked in the mainline.

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Design of a PWM DC-DC Boost Converter IC for Mobile Phone Flash (휴대전화 플래시를 위한 PWM 전류모드 DC-DC converter 설계)

  • Jung, Jin-Woo;Heo, Yun-Seok;Park, Yong-Su;Kim, Nam-Tae;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.6
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    • pp.2747-2753
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    • 2011
  • In this paper, a PWM current-mode DC-DC boost converter for mobile phone flash application has been proposed. The converter which is operated with 5 Mhz high switching frequency is capable of reducing mounting area of passive devices such as inductor and capacitor, consequently is suitable for compact mobile phones. This boost converter consists of a power stage and a control block. Circuit elements of the power stage are inductor, output capacitor, MOS transistors and feedback resistors. Meanwhile, the control block consists of pulse width modulator, error amplifier, oscillator etc. Proposed boost converter has been designed and verified in a $0.5\;{\mu}m$ 1-poly 2-metal CMOS process technology. Simulation results show that the output voltage is 4.26 V in 3.7 V input voltage, output current 100 mA which is larger than 25 ~ 50 mA in conventional 500 Khz driven converter when the duty ratio is 0.15.

PR (1 2 2 1) Signal Decoding for DVD using the Circular Analog Parallel Circuits (순환형 아날로그 병렬 회로망 구조를 이용한 DVD용 PR (1 2 2 1) 신호의 디코딩)

  • Son Hongrak;Kim Hyonjeong;Kim Hyongsuk;Lee Jeongwon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.1 s.343
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    • pp.17-26
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    • 2006
  • The analog Viterbi decoder for the PR (1 2 2 1) which is used for BVD read channel is designed with circular analog parallel circuits. Since the inter symbol interference is serious problem in the high density magnetic storage device or DVD, the PRML technology is normally employed for the purpose of minimizing the decoding error. The feature of the PRML technology is with the multi-level coding according to the predetermined combining rule among the neighboring symbols and with the decoding according to the known combining rule. Though the conventional PRML technology is implemented with the digital circuits, the recent trend towards this end is with the utilization of the analog circuits due to the requirements of higher speed and lower power in the DVD read channel. In this study, the Viterbi decoder which is the bottleneck of the PRML implementation is designed with the analog parallel circuit structure. The designed Viterbi decoder for the PR (1 2 2 1) signal shows 3 times faster in the speed and 1/3 times less in the power consumption than thoseoftheconventionaldigitalcounterpart.