• Title/Summary/Keyword: circuit power

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Thermal Characteristics Investigation of 6U CubeSat's Deployable Solar Panel Employing Thermal Gap Pad (열전도 패드가 적용된 6U 큐브위성용 태양전지판의 열적 특성 분석)

  • Kim, Hye-In;Kim, Hong-Rae;Oh, Hyun-Ung
    • Journal of Aerospace System Engineering
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    • v.14 no.3
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    • pp.51-59
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    • 2020
  • In the case of cubesat, a PCB-based deployable solar panel advantageous in terms of weight reduction and electrical circuit design is widely used considering the limited weight and volume of satellites. However, because of the low thermal conductivity of PCB, there is a limit relative to heat dissipation. In this paper, the thermal gap pad is applied to the contact between the PCB-based solar panel and the aluminum stiffener mounted on the outside of the panel. Thus, the heat transfer from the solar cell to the rear side of the panel is facilitated. It maximizes the heat dissipation performance while maintaining the merits of PCB panel, and thus, it is possible to improve the power generation efficiency from reducing the temperature of the solar cell. The effectiveness of the thermal design of the 6U cubesat's deployable solar panel using the thermal gap pad has been verified through on-orbit thermal analysis based on the results, compared with the conventional PCB-based solar panel.

5-bit FLASH A/D Converter Employing Time-interpolation Technique (시간-보간법을 활용한 5-bit FLASH ADC)

  • Nam, Jae-Won;Cho, Young-Kyun
    • Journal of Convergence for Information Technology
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    • v.11 no.9
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    • pp.124-129
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    • 2021
  • A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.

Radiation measurement and imaging using 3D position sensitive pixelated CZT detector

  • Kim, Younghak;Lee, Taewoong;Lee, Wonho
    • Nuclear Engineering and Technology
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    • v.51 no.5
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    • pp.1417-1427
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    • 2019
  • In this study, we evaluated the performance of a commercial pixelated cadmium zinc telluride (CZT) detector for spectroscopy and identified its feasibility as a Compton camera for radiation monitoring in a nuclear power plant. The detection system consisted of a $20mm{\times}20mm{\times}5mm$ CZT crystal with $8{\times}8$ pixelated anodes and a common cathode, in addition to an application specific integrated circuit. The performance of the various radioisotopes $^{57}Co$, $^{133}Ba$, $^{22}Na$, and $^{137}Cs$ was evaluated. In general, the amplitude of the induced signal in a CZT crystal depends on the interaction position and material non-uniformity. To minimize this dependency, a drift time correction was applied. The depth of each interaction was calculated by the drift time and the positional dependency of the signal amplitude was corrected based on the depth information. After the correction, the Compton regions of each spectrum were reduced, and energy resolutions of 122 keV, 356 keV, 511 keV, and 662 keV peaks were improved from 13.59%, 9.56%, 6.08%, and 5%-4.61%, 2.94%, 2.08%, and 2.2%, respectively. For the Compton imaging, simulations and experiments using one $^{137}Cs$ source with various angular positions and two $^{137}Cs$ sources were performed. Individual and multiple sources of $^{133}Ba$, $^{22}Na$, and $^{137}Cs$ were also measured. The images were successfully reconstructed by weighted list-mode maximum likelihood expectation maximization method. The angular resolutions and intrinsic efficiency of the $^{137}Cs$ experiments were approximately $7^{\circ}-9^{\circ}$ and $5{\times}10^{-4}-7{\times}10^{-4}$, respectively. The distortions of the source distribution were proportional to the offset angle.

Fabrication and Chracteristics of Cutting Cell with Various Laser Conditions (다양한 레이저 조건에 따른 컷팅셀 제작 및 특성 분석)

  • Park, Jeong Eun;Kim, Dong Sik;Choi, Won Seok;Jang, Jae Joon;Lim, Dong gun
    • Journal of the Korean Solar Energy Society
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    • v.39 no.3
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    • pp.9-17
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    • 2019
  • Laser cutting cell of solar cells can achieve high voltage and efficiency through more array than conventional 6 inch cell compared to same area. In this study, we fabricated c-Si cutting cell with various lasers and laser conditions such as power, speed, and number of times. In the case of picosecond laser, excellent surface characteristics were obtained due to small surface defects and low thermal damage at the output of 20W and the speed of 100 mm/s. However, it is not possible to fabricate a cutting cell having good characteristics due to nonuniform cutting inside the wafer when the processing for forming a cutting cell is not sufficiently performed. For nanosecond lasers, the best wafer characteristics were obtained for fabrication of excellent cutting cells at a frequency of 500 kHz and a laser speed of 100 mm/s. However, the nanosecond laser has not been processed sufficiently in the condition of a number of times. As a result, it was confirmed that the wafer thickness was cut by $63{\mu}m$ of the cell thickness of $170{\mu}m$ in the condition of five times of laser process. It was found that more than 30% of the wafer thickness had to be processed to fabricate the cutting cell. After cutting the 6-inch cell having the voltage of 0.65 V, we obtained the voltage of about 0.63 V.

Development of Embedded Board for Construction of Smart Factory (스마트 팩토리 구축을 위한 임베디드 보드 개발)

  • Lee, Yong-Min;Lee, Won-Bog;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.23 no.3
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    • pp.1092-1095
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    • 2019
  • In this paper, we propose the development of an embedded board for construction of smart factory. The proposed embedded board for construction of smart factory consists of main module, ADC module, I/O module. Main module is a main calculating device which includes communication pard that allows interface with external device with using industrial protocol and is ported operating system makes board operating into. ADC module takes part in transferring digital signal has converted from electrical signal to the main module from the external sensor which is installed on the field. I/O module is an input and output module which transfers to the main module about a status, alarm, command signal of field device and it has a function that blocks external noises from field device with isolation circuit into it. In order to evaluate the performance of the proposed embedded board for construction of smart factory, it has been tested by an authorized testing institute. As a result, quantity of interacting protocol was 5, speed of hardware clock synchronization was under 10us and operating time of battery without source power was over 8 hours. It produced the same result as the world's highest level.

Design of digitally controlled CMOS voltage mode DC-DC buck converter for high resolution duty ratio control (고해상도 듀티비 제어가 가능한 디지털 제어 방식의 CMOS 전압 모드 DC-DC 벅 변환기 설계)

  • Yoon, KwangSub;Lee, Jonghwan
    • Journal of IKEEE
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    • v.24 no.4
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    • pp.1074-1080
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    • 2020
  • This paper proposes a digitally controlled buck converter insensitive to process, voltage and temperature and capable of three modes of operation depending on the state of the output voltage. Conventional digital-controlled buck converters utilized A/D converters, counters and delay line circuits for accurate output voltage control, resulting in increasing the number of counter and delay line bits. This problem can be resolved by employing the 8-bit and 16-bit bidirectional shift registers, and this design technique leads a buck converter to be able to control duty ratio up to 128-bit resolution. The proposed buck converter was designed and fabricated with a CMOS 180 nano-meter 1-poly 6-metal process, generating an output voltage of 0.9 to 1.8V with the input voltage range of 2.7V to 3.6V, a ripple voltage of 30mV, and a power efficiency of up to 92.3%. The transient response speed of the proposed circuit was measured to be 4us.

Design and Implementation of Portable Electrostatic Meter Applicable to Industrial Site (산업 현장에 적용할 수 있는 휴대형 정전기 측정기 설계 및 구현)

  • Jang, Mun-Seok;Lee, Eung-Hyuk
    • Journal of the Korean Society of Industry Convergence
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    • v.23 no.6_2
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    • pp.971-977
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    • 2020
  • In this paper, We propose a portable electrostatic meter which can measure high voltage static electricity caused by friction to prevent fire or explosion accidents in grinding, crushing, power injection, transport, filling, dust removal, painting, and foreign matter removal processes. The proposed device not only shows static electricity strength in 4 steps with respect to distance and voltage but also gives warning with a buzzer, on process facilities that are likely to generate high voltage static electricity due to friction. The device is implemented by filtering the signal detected by the wireless antenna, amplifying the signal by 6 times, and passing the signal through the integrator circuit. Tests are carried out with an electrostatic discharge simulator. And the results show that 4 LEDs are turned on at the distance of 10cm, 3 LEDs at 12cm, 2 LEDs at 13cm, and 1 LED at 15cm, when a fixed voltage of 500V is given. And also, the tests show that the static electricity can be detected at 5cm on 100V, 10cm on 200V, 15cm on 500V, 20cm on 1000V, and 25cm on 1500V. We expect to reduce accidents caused by static electricity by allowing safety managers on fields where fire or explosion accidents can happen to monitor static electricity.

The characteristic of Cu2ZnSnS4 thin film solar cells prepared by sputtering CuSn and CuZn alloy targets

  • Lu, Yilei;Wang, Shurong;Ma, Xun;Xu, Xin;Yang, Shuai;Li, Yaobin;Tang, Zhen
    • Current Applied Physics
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    • v.18 no.12
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    • pp.1571-1576
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    • 2018
  • Recent study shows that the main reason for limiting CZTS device performance lies in the low open circuit voltage, and crucial factor that could affect the $V_{oc}$ is secondary phases like ZnS existing in absorber layer and its interfaces. In this work, the $Cu_2ZnSnS_4$ thin film solar cells were prepared by sputtering CuSn and CuZn alloy targets. Through tuning the Zn/Sn ratios of the CZTS thin films, the crystal structure, morphology, chemical composition and phase purity of CZTS thin films were characterized by X-Ray Diffraction (XRD), scanning electron microscopy (SEM) equipped with an energy dispersive spectrometer (EDS) and Raman spectroscopy. The statistics data show that the CZTS solar cell with a ratio of Zn/Sn = 1.2 have the best power convention efficiency of 5.07%. After HCl etching process, the CZTS thin film solar cell with the highest efficiency 5.41% was obtained, which demonstrated that CZTS film solar cells with high efficiency could be developed by sputtering CuSn and CuZn alloy targets.

Densification and Electrochemical Properties of YSZ Electrolyte Decalcomania Paper for SOFCs by Decalcomania (전사법으로 제조한 SOFC용 YSZ 전해질 전사지의 치밀화 및 전기화학적 특성)

  • Cho, Hae-Ran;Choi, Byung-Hyun;An, Yong-Tae;Baeck, Sung-Hyeon;Roh, Kwang-Chul;Park, Sun-Min
    • Korean Journal of Metals and Materials
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    • v.50 no.9
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    • pp.685-690
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    • 2012
  • Decalcomania is a new method for SOFCs (solid oxide fuel cells) unit cell fabrication. A tight and dense $5{\mu}m$ Yttria-stabilized zirconia (8YSZ) electrolyte layer on anode substrate was fabricated by the decalcomania method. After 8YSZ as the electrolyte starting material was calcined at $1200^{\circ}C$, the particle size was controlled by the attrition mill. The median particle size (D50) of each 8YSZ was $39.6{\mu}m$, $9.30{\mu}m$, $6.35{\mu}m$, and $3.16{\mu}m$, respectively. The anode substrate was coated with decalcomania papers which were made by using 8YSZ with different median particle sizes. In order to investigate the effect of median particle sizes and sintering conditions on the electrolyte density, each sample was sintered for 2, 5 and 10 h, respectively. 8YSZ with a median particle size of $3.16{\mu}m$ which was sintered at $1400^{\circ}C$ for 10 had the highest density. With this 8YSZ, a SOFCs unit cell was manufactured with a $5{\mu}m$ layer by the decalcomania method. Then the unit cell was run at $800^{\circ}C$. The Open Circuit Voltage (OCV) and Maximum power density (MPD) was 1.12 V and $650mW/cm^2$, respectively.

Analysis on the Light Source Efficiency of CCFL and LED Monitors (CCFL 및 LED 모니터 광원 효율 분석)

  • Shin, Hee-Woo;Yoo, Jae-Soo
    • The Journal of the Korea Contents Association
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    • v.21 no.6
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    • pp.44-50
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    • 2021
  • In this paper, we analyze the efficiency of light sources of CCFL and LED monitors. Cold Cathode Fluorescent Lamp (CCFL), which is widely used as a light source for LCD display, supplies a high voltage of 1,200[V] or more when it is initially driven. In addition, a constant normal voltage of 400 ~ 800[V] after lighting, and 3 ~ 6[ mA] is needed for a power circuit that can stabilize the current. Applying a high voltage causes a lot of stress on the inverter and generates a lot of heat in the cold cathode lamp, causing significant damage to the BLU (Back Light Unit), resulting in a burning phenomenon, which causes the screen to output normal colors when outputting the screen. We can not see the yellow output and the screen darkened. Therefore, in order to prevent such a symptom in advance, efficiency can be increased by using a Light Emitting Diode (LED) as the light source of the LCD display instead of a cold cathode fluorescent lamp (CCFL). As a result, it is shown that the LED method outperforms the CCFL method.