• Title/Summary/Keyword: circuit model

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The Study of Circuit Model Parameter Generation Using Device Simulation (소자 시뮬레이션을 이용한 Circuit Model Parameter 생성에 대한 연구)

  • 이흥주
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.4 no.3
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    • pp.177-182
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    • 2003
  • In the case of the flash memory, various kinds of transistors and the wide range of operation voltage are necessary to achieve the read/write operations. Therefore, the characteristics of transistors are measured in the silicon for the circuit design, and the test vehicle run must be processed. In this study, an efficient design flow is suggested using TCAD tools. The test vehicle is replaced with well-calibrated TCAD simulation. First, the calibration methodology is introduced and tested for flash memory device. The calibration errors are less than 5% of a full chip operation, which is accepted by the designers. The results of the calibration were used to predict I-V curves and model parameter of the various transistors for the design of flash device.

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An equivalent Circuit Model of Transformer Coupled Plasma Source (축전 용량이 고려된 평판형 유도 결합 플라즈마 원의 등가회로 모델)

  • Kim, Jeong-Mi;Kwon, D.C.;Yoon, N.S.
    • Proceedings of the KIEE Conference
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    • 2002.07c
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    • pp.1760-1762
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    • 2002
  • In this work we develop an equivalent circuit model of TCP(transformer coupled plasma) source and investigate matching characteristic. The developed circuit model includes transmission line, standard-type impedance matching network and displacement current in the plasma source. The impedance of TCP is calculated by previously developed program for various source parameters and dependance of components of matching impedance on the value of source impedance is investigated.

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Compensation of Equivalent Circuit Model of TE011 Mode Cylindrical Cavity Filter

  • Ryu, Nam-Young;Lee, Jeong-Hae
    • Journal of electromagnetic engineering and science
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    • v.2 no.2
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    • pp.100-104
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    • 2002
  • A proper equivalent circuit model for coupling iris has been derived in order to compensate the length of cavity in a $TE_{011}$TEX> mode cylindrical cavity filter. A method to resolve the difference in bandwidth and feature or ripple systematically has been proposed. This method can be applied to other types of waveguide cavity filter.

Design of Optical FSK Transmitter Using LD-FM Circuit Model (LD-FM 회로모델을 이용한 광 FSK 송신기 설계)

  • 소준호;박상영;이규송;임호근;김성환;홍완혜
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.4
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    • pp.612-619
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    • 1990
  • In this paper, a design method of optical FSK transmitter is described using LD-FM circuit model. In the design of optical FSK transmitter, an optimum bias current was chosen using LD-FM circuit model, and an unequalized FM transfer function was determined at this current. The equalizers that can make this transfer function uniform were designed by use of a simple passive network. For the designed optical FSK transmitter, the pulse-transient and small-signal frequency-deviation responses were simulated and discussed.

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Highly Robust AHHVSCR-Based ESD Protection Circuit

  • Song, Bo Bae;Koo, Yong Seo
    • ETRI Journal
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    • v.38 no.2
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    • pp.272-279
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    • 2016
  • In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit - (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.

Over-Temperature Protection Circuit Modeling Using MOSFET Rds(on) Temperature-Resistance Characteristics (MOSFET Rds(on) 온도-저항 특성을 이용한 과열보호회로 모델링)

  • Choi, Nak-Gwon;Lee, Sang-Hoon;Kim, Hyoung-Woo;Kim, Ki-Hyun;Seo, Kil-Soo;Kim, Nam-Kyun
    • Proceedings of the KIEE Conference
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    • 2005.07d
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    • pp.3019-3021
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    • 2005
  • In this paper we suggest a novel temperature detection method utilized in direct over-temperature protection circuit modeling. The suggested model detects temperature variation using Rds(on) characteristics of MOSFET, while the conventional methods are using extra devices such as a temperature sensor or an over-temperature detection transistor. The temperature-dependant MOSFET model is implemented using Spice ABM(Spice Analog Behavior Model). The direct over-temperature protection circuit was designed including it. We verified effectiveness of the temperature dependant Rds(on) model characteristics and performance of the direct over-temperature protection circuit on PSpice simulation

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Analysis of Appropriate Parameters for Piezoelectric Ceramic Utilization by Using BVD Model

  • Jeerapan, Chalermchai;Sriratana, Witsarut;Julsereewong, Prasit;Kummool, Sart
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.2067-2070
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    • 2005
  • This paper presents an approach to evaluate the appropriate parameters for Piezoelectric ceramic utilization by adopting Impedance Method. Butterworth Van Dyke model (BVD) is considered to use as an equivalent circuit of Piezoelectric ceramic in case of no load. The experimental results from this model will be compared with the results from a circular Piezoelectric ceramic with 4.8 cm. diameter and 3 mm. thickness. The Thickness Mode vibration measured by Impedance Analyzer model 4192A can be analyzed from 1Hz to 13MHz for calculating and analyzing parameters at resonance frequency and anti-resonance frequency. These parameters are evaluated to design the efficient circuit for Piezoelectric ceramic utilization to obtain the optimal efficiency.

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Signal line potential variation analysis and modeling due to switching noise in CMOS integrated circuits (CMOS 집적회로에서 스위칭 노이즈에 의한 신호선의 전압변동 해석 및 모델링)

  • 박영준;김용주;어영선;정주영;권오경
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.7
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    • pp.11-19
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    • 1998
  • A signal line potential variation due to the delta-I noise was physically investigated in CMOS integrated circuits. An equivalent circuit for the noise analysis was presented. The signal line was modeled as segmented RC-lumped circuits with the ground noise. Then the equivalent circuit was mathematically analyzed. Therebvy a new signal line potential variation model due to the switching mosie was developed. Th emodel was verified with 0.35.mu.m CMOS deivce model parameters. The model has an excellent agreement with HSPICE simulation. Thus the proposed model can be dirctly employed in the industry to design the high-performance integrted circuit design as well as integrated circuit package design.

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Analytic Model of Spin-Torque Oscillators (STO) for Circuit-Level Simulation

  • Ahn, Sora;Lim, Hyein;Shin, Hyungsoon;Lee, Seungjun
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.1
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    • pp.28-33
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    • 2013
  • Spin-torque oscillators (STO) is a new device that can be used as a tunable microwave source in various wireless devices. Spin-transfer torque effect in magnetic multilayered nanostructure can induce precession of magnetization when bias current and external magnetic field are properly applied, and a microwave signal is generated from that precession. We proposed a semi-empirical circuit-level model of an STO in previous work. In this paper, we present a refined STO model which gives more accuracy by considering physical phenomena in the calculation of effective field. Characteristics of the STO are expressed as functions of external magnetic field and bias current in Verilog-A HDL such that they can be simulated with circuit-level simulators such as Hspice. The simulation results are in good agreement with the experimental data.

Experimental Characterization and Signal Integrity Verification of Interconnect Lines with Inter-layer Vias

  • Kim, Hye-Won;Kim, Dong-Chul;Eo, Yung-Seon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.11 no.1
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    • pp.15-22
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    • 2011
  • Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.