• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1125-1134
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• 2011

In this paper a wideband frequency synthesizer is designed for DTV tuners using a $0.18{\mu}m$ CMOS process. It satisfies the DTV frequency band(48~1675MHz). A scheme is proposed to cover the full band using only one VCO and reliable broadband characteristics are achieved by reducing the variations of VCO gains and frequency steps. The simulation results show that the designed VCO has frequency range of 1.85~4.22GHz, phase noise at 4.22GHz of -89.7dBc/Hz@100kHz, gains of 62.4~95.8MHz/V(${\pm}21.0%$) and frequency steps of 22.9~47.9MHz(${\pm}35.3%$). The designed VCO has a phase noise of -89.75dBc/Hz at 100kHz offset. The designed synthesizer has a lock time less than $0.15{\mu}s$. The measured VCO tuning range is 2.05~3.4GHz. The frequency range is shifted down but still satisfy the target range owing to the design for enough margin. The designed circuit consumes 23~27mA from a 1.8V supply, and the chip size including PADs is $2.0mm{\times}1.5mm$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1868-1876
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• 2010

In this paper, we design a 256-bit EEPROM IP using only logic process-based devices. We propose EEPROM core circuits, a control gate (CG) and a tunnel gate (TG) driving circuit, to limit the voltages between the devices within 5.5V; and we propose DC-DC converters : VPP (=+4.75V), VNN (-4.75V), and VNNL (=VNN/3) generation circuit. In addition, we propose switching powers, CG_HV, CG_LV, TG_HV, TG_LV, VNNL_CG, VNNL_TG switching circuit, to be supplied for the CG and TG driving circuit. Simulation results under the typical simulation condition show that the power consumptions in the read, erase, and program mode are $12.86{\mu}W$, $22.52{\mu}W$, and $22.58{\mu}W$ respectively. Furthermore, the manufactured test chip operated normally and generated its target voltages of VPP, VNN, and VNNL as 4.69V, -4.74V, and -1.89V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2237-2246
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• 2012

A bias circuit required for an oral sensor is manufactured inside the oral sensor chip to reduce its size and cost. The proposed DC-DC converter supplies the required reference and bias currents for their corresponding regulators by using IREF of the reference current generator. Their target voltages of the voltage regulators are regulated by the negative mechanism by generating their reference voltages required for their corresponding regulators. In addition, a constant current IB0/IB1 is supplied by being mirrored by a current mirror ratio and then VREF is generated. It is confirmed by measurements that the average volatge, ${\sigma}$, and $4{\sigma}$ of the designed DC-DC converter for intra oral sensors with a $0.18{\mu}m$ X-ray CMOS process are within their required ranges. And the line-pair pattern image shows a high-resolution characteristic without blurring. Also, a good oral image can be obtained.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.3
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• pp.50-56
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• 2010

In this paper, compact broad-band antenna using circular spiral slot and CPW (coplanar waveguide) feed is proposed. The proposed antenna is designed on the same plane of the substrate by using CPW fed structure, archimediean spiral slot structure. So it was achieved both the size of compact antenna and the broad band. A archimediean spiral slot structure is introduced for resonance of medium band operation. The distances of a CPW feeder line and a ground plane are modified for impedance matching and lower/higher band operation. The proposed antenna has a compact size ($8mm\;{\times}\;13mm$) and it is etched on the FR-4 (relative dielectric constant 4.4, thickness 0.8mm) dielectric substrate. The simulated impedance bandwidth (VSWR $\leq$ 2) and maximum gain of the proposed antenna are 5.98GHz (4.1GHz ~ 10.08GHz) and 3.97dBi, respectively. The measured impedance bandwidth (VSWR $\leq$ 2) and maximum gain of the proposed antenna are 6.02GHz (4.48GHz ~ 10.5GHz) and 2.68dBi, respectively. The simulation and measured result shows good impedance matching and radiation pattern over the interesting frequency bands. It can be applied to antenna of broad-band wireless communication system.

• Journal of the Korea Society of Computer and Information
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• v.17 no.4
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• pp.1-9
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• 2012

As we are turnning into the aged society, accidents by falling down are increasing in the aged people's group. In this paper, we design the system with the 3-Axis acceleration sensor which is composed by a single chip. The body activity signal is measured with the signal detector and RF communicator in this proposed system and the and falling by the entering signal pattern analysis with 3-Axis acceleration sensor. For the RF communication, we are using nRF24L01p and 8bits ATmega uC for the processor. The error of energy expenditure estimation between motor driven treadmill and proposed a body activity module was 7.8% respectively. Human activities and falling is monitored according to analyze and judge the critical value of the Signal Vector. as falled down if they don't turn off the alarm after specific period and the aged person's after falling down activities are their position and more.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1927-1934
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• 2016

In this paper, we proposed a I-gate n-MOSFET (n-type Metal Oxide Semiconductors Field Effect Transistor) structure in order to mitigate a radiation-induced leakage current path in an isolation oxide interface of a silicon-based standard n-MOSFET. The proposed I-gate n-MOSFET structure was designed by using a layout modification technology in the standard 0.18um CMOS (Complementary Metal Oxide Semiconductor) process, this structure supplements the structural drawbacks of conventional radiation-tolerant electronic device using layout modification technology such as an ELT (Enclosed Layout Transistor) and a DGA (Dummy Gate-Assisted) n-MOSFET. Thus, in comparison with the conventional structures, it can ensure expandability of a circuit design in a semiconductor-chip fabrication. Also for verification of a radiation-tolerant characteristic, we carried out M&S (Modeling and Simulation) using TCAD 3D (Technology Computer Aided Design 3-dimension) tool. As a results, we had confirmed the radiation-tolerant characteristic of the I-gate n-MOSFET structure.

• Journal of Navigation and Port Research
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• v.27 no.4
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• pp.443-447
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• 2003

In this work. using 0.2 GaAs modulation doped FET(MODFET), a high performance DBS downconverter MMIC was developed for direct broadcasting satellite (DBS) application. Without LNA, the downconverter MMIC showed a very low noise of 4.8 dB, which is lower by 3 dB than conventional ones. A low LO power of -10 dBm was required for the normal DBS operation of the downconverter MMIC. which reduced the power consumption via a removal of LO amplifier on MMIC. It required only a low power consumption of 175 mW, which is lower than 70 percent of conventional ones. The LO leakage power at IF output was suppressed to a lower level than 30 dBm, which removes a bulky LO rejection filter on a board. The fabricated chip, which include a mixer, If amplifiers. LO rejection filter, and active balun, exhibited a small size of $0.84{\times}0.9\textrm{mm}^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2366-2373
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• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

• Korean Security Journal
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• no.13
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• pp.145-168
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• 2007

Like to change to the information-oriented society, the guard service needs to be changed. The communication and hardware technology develop rapidly and according to the internet environment change from cable to wireless, modern person can approach every kinds of information service using wireless communication machinery which can be moved such as laptop, computer, PDA, mobile phone and so on, LBS field which presents the needing information and service at anytime, anywhere, and which kinds of device expands it's territory all the more together with the appearance of ubiquitous concept. LBS use the chip in the mobile phone and make to confirm the position of the joining member anytime within several tens centimeters to hundreds meters. LBS can be divided by the service method which use mobile communication base station and apply satellite. Also each service type can be divided by location chase service, public safe service, location based information service and so on, and it is the part which will plan with guard service development. It will be prospected 8.460 hundred million in 2005 years and 16.561 hundred million in 2007 years scale of market. Like this situation, it can be guessed that the guard service has to change rapidly according to the LBS application. Study method chooses documentary review basically, and at first theory method mainly uses the second documentary examination which depends on learned journal and independent volume which published in the inside and the outside of the country, internet searching, other kinds of all study report, statute book, thesis which published at public order research institute of the Regional Police Headquarter, police operation data, data which related with statute, documents and statistical data which depend on private guard company and so on. So the purpose of the study gropes in accordance with the LBS application, and present the problems and improvement method to analyze indirect of manager side of operate guard adaptation service of LBS, government side which has to activate LBS, systematical, operation management, manpower management and education training which related with guard course side which has to study and educate in accordance with application of the new guard service, as well as intents to excellent quality service of guard.