• Journal of Institute of Control, Robotics and Systems
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• v.12 no.6
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• pp.530-538
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• 2006

DSP chip parameters of a digital hearing aid (HA) should be optimally selected or fitted for hearing impaired persons. The more precise parameter fitting guarantees the better compensation of the hearing loss (HL). Digital HAs adopt DSP chips for more precise fitting of various HL threshold curve patterns. A specific DSP chip such as Gennum GB3211 was designed and manufactured in order to match up to about 4.7 billion different possible HL cases with combination of 7 limited parameters. This paper deals with a digital HA fitting program which is developed for optimal fitting of GB3211 DSP chip parameters. The fitting program has completed features from audiogram input to DSP chip interface. The compensation effects of the microphone and the receiver are also included. The paper shows some application examples.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.376-379
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• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.

• Journal of information and communication convergence engineering
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• v.6 no.2
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• pp.122-128
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• 2008

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.2
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• pp.193-197
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• 1997

In this paper, we propose a new PN chip clock generator which employs two synchronous counters to achieve precise phase control of chip clock. In a CDMA code acquisition and tracking system, the PN chip clock is required to operate highly reliable without any glitch even under harsh environment condition such as temperature and voltage fluctu-aliens. The digital implementation of the proposed PN chip clock generator imparts it with much desired reliability. Since the proposed chip clock generator can be easily controlled into one of the states: free running, phase advance, and delay state, it can be applied to data processing as well as code synchronization. We have done FPGA implementation of the proposed logic and have verified its satisfactory operation up to 50 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.8
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• pp.1564-1573
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• 2007

Bulk of toner residual quantity detection return trip conglutinated in toner of using printer current is comparative big state by using PCB substrate, therefore is incongruent to use in light weight print miniaturized more. Return trip this development miniaturizes such as this by doing one chip competitive product develop chip has to be conglutinated compulsorily in toner used to printer announced since 2005 years. Therefore, demand of chip to be used in forward revival market may be thriving. Production of revival toner is impossible by chip conglutinated to printer to meaning that manage information of toner cut ridge that universal laser printer makers are used in printer and do customer service. In this paper, we develops chip conglutinated compulsorily to produce revival toner.

• Journal of electromagnetic engineering and science
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• v.2 no.1
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• pp.1-4
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• 2002

Performance improvement of the DS-CDMA system by the spectrum-overlap is important for better service quality or more system capacity. In this paper, an analysis thor capacity improvement is newly considered when the Lanczos chip waveform is used for the spectrum-overlapped DS-CDMA system. RC(relative capacity) is the ratio of the capacity of overlapping system to that of non-overlapping system, which is used for the expression of the capacity improvement. The optimal overlapping ratio is numerically found to make the maximum capacity improvement When the rectangular chip waveform is used far the overlapping system, maximum capacity improvement is increased by about 10% at the required BER=$10^{-3}$TEX> and the optimal overlapping ratio is 1.23. When the 95 % power bandwidth is considered for the Lanczos chip waveform, maximum capacity improvement is increased by 34.4% at overlapping ratio of 1.55 when the required BER is $10^{-3}$TEX>. The lower required BER far the better communication quality makes gradually smaller capacity improvement.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.122-134
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• 1994

Design of a heuristic algorithm for high level synthesis of multichip architecture is presented in this paper. Considering the design constraints: individual chip area, I/O pin counts, chip-to-chip interconnection counts, interchip communication delay, and chip latecy, the proposed system automatically generates pipelined multichip architectures from behavioral descriptions. For efficient mulichip synthesis, a new methodology is proposed, which performs partitioning and schedulting of SFG into multichip architectures simultaneously. Experimental results for several benchmark programs show that the systems can be used for designing multichip hardware efficiently.

• Journal of electromagnetic engineering and science
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• v.14 no.1
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• pp.43-45
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• 2014

We propose a printed circuit board (PCB)-embedded antenna for millimeter-wave chip-to-chip communication. The antenna is 0.18 mm in height which is 1/20 wavelength at 80 GHz. In order to realize such a low profile, a zeroth-order resonator antenna with a periodic array of four unit cells is employed, and its geometry is optimized to cover an 8-GHz bandwidth from 76 to 84 GHz. With this;the antenna is capable of radiating in a direction parallel to the board length despite the short distance between the ground and the radiator. Simulation and measurement results show that the optimized design has low reflection coefficients and consistent radiation patterns throughout the target bandwidth.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.3
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• pp.19-24
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• 1999

The multilayer chip band pass filter for mobile communication is fabricated and designed. The size, insertion loss, center frequency and band width of multilayer chip filter are 4.5$\times$4.4$\times$1.8[mm], 3.0[dB] and 700[MHz]$\pm$15[MHz] respectively. The chip filter using $BiNbO_4$with CuO 0.06wt% +$V_2O_5$.lwt% was fabricated by screen printing with Ag electrode after tape casting. Insertion loss and center frequency of the fabricated chip filter are 2.58[dB] and 692.5$\pm$15[MHz] respectively. The center frequency was lower 7.5[MHz] than design result, but other characteristics of chip filter were similar to the ruts ultras of design result.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.891-892
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• 2006

An obstacle is an element for power to small and slim the existing portable communication set. Developed Inductor for Chip-type electric power in needs to solve this. Stack applied Process, and used gap of a magnetic path, and made a height of an element to 1.0T or below, and this development commodity did product for saturation prevention to materials of silver. Saturation current characteristic of Chip-type inductor was low compare with winding-type inductors, but bulk against performance were had superior excellence. Chip-type inductor can raise performance per unit volume compared with the existing inductors at these papers. Therefore, acceleration can get growth of small and slim of a mobile product done, and expect.