• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.65-72
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• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.

• Korean Chemical Engineering Research
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• v.47 no.1
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• pp.1-10
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• 2009

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional chip cannot be a solution for the enhancement of the semiconductor chip technology due to an increase in RC delay among interconnects. To address this problem, a new technology - "3 dimensional (3D) IC chip stack" - has been emerging. For the integration of the technology, several new key unit processes (e.g., silicon through via, wafer thinning and wafer alignment and bonding) should be developed and much effort is being made to achieve the goal. As a result of such efforts, 4 and 8 chip-stacked DRAM and NAND structures and a system stacking CPU and memory chips vertically were successfully developed. In this article, basic theory, configurations and key unit processes for the 3D IC chip integration, and a current tendency of the technology are explained. Future opportunities and directions are also discussed.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.2
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• pp.102-110
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• 2009

The memory wall is the growing disparity of speed between CPU and memory outside the CPU chip. An economical solution is a memory hierarchy organized into several levels, such as processor registers, cache, main memory, disk storage. We introduce a novel memory hierarchy optimization technique in Linux based embedded systems using on-chip SRAM for the first time. The optimization technique allocates On-Chip SRAM to the code/data that selected by programmers by using virtual memory systems. Experiments performed with nine applications indicate that the runtime improvements can be achieved by up to 35%, with an average of 14%, and the energy consumption can be reduced by up to 40%, with an average of 15%.

• ETRI Journal
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• v.31 no.2
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• pp.111-120
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• 2009

Network-on-chip (NoC) architecture provides a highper-formance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in $6{\times}6$6, $8{\times}8$, and $10{\times}10$ mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit-switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.

• The Journal of Korean Medicine
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• v.24 no.2
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• pp.148-158
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• 2003

Backgrounds & Objectives: In many recent studies, molecular biological methods have been used to investigate the role of cytokines in pathogenesis and new therapeutic targets of asthma. Recently, as a method of research on the gene expression, they are applying another method which assays multiple gene expressions at the same time by the microarray. In this study, the antioxidant effect, the inhibitory effect against interleukin-4 and the effect on the CD/cytokine gene expression in PBMC (peripheral blood mononuclear cells) was evaluated by using cDNA microarray chip of Chungsangboha-tang. Methods: Experimental studies were performed for the antioxidant effect of Chungsangboha-tang on DPPH (1, 1-diphenyl-2-picrylhydrazyl) solution, for the IL-4-inhibiting effect on BALB/c mouse spleen, and for the gene expression effect on PBMC (peripheral blood mononuclear cells) with microarray. Results: Chungsangboha-tang showed antioxidant effect dose-dependently. Chungsangboha-tang inhibited interleukin-4 dose-dependently and showed significant difference in 10ug/ml and 100ug/ml of test groups. There was no 2 more times upregulated genes than in the control group by using cDNA microarray chip of Chungsangbohn-tang, but there were 140%-200% upregulated genes. There was no 2 more times downregulated genes than in the control group by using cDNA microarray chip of Chungsangboha-Tang, but there was 50%-75% downregulated genes. Conclusions: This study showed that Chungsangboha-tang has an antioxidant effect and inhibition of Interleukin-4, but further studies are necessary with microarray.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• Journal of Biosystems Engineering
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• v.15 no.4
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• pp.328-338
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• 1990

The objective of this study was to develop automatic systems of nutrient solution management for optimal nutrient solution environment and labor saving in water culture which enables factory crop production. In this study, an automatic control system and its driving program are developed to prepare, supply, and recover nutrient solution and to keep the optimal solution concentration level using microcomputers. Based on this study, the following conclusions are obtained: 1. The concentration measured by the system using oscillating circuit designed and built in this study, gave good agreements with the actual nutrient solution. 2. In water culture, the period of 12 hours for measuring concentration, pH, and temperature of the nutrient solution was optimum. Addition of control solution due to the decrease of the nutrient solution concentration is required in every 3 to 5 days. 3. It is estimated that the period of the whole solution change is 15 days, however, further research is needed to assure it. In addition, this period must be shortened in the future. 4. Both the hardware and software of the developed optimal nutrient solution control system in the water culture are working very well, however, it is necessary to develop a more economical one-chip micro controller to substitute for the microcomputer.

• Korea-Australia Rheology Journal
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• v.17 no.4
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• pp.207-215
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• 2005

We present a finite difference solution for electrokinetic flow in rectangular microchannels encompassing Navier's fluid slip phenomena. The externally applied body force originated from between the nonlinear Poisson-Boltzmann field around the channel wall and the flow-induced electric field is employed in the equation of motion. The basic principle of net current conservation is applied in the ion transport. The effects of the slip length and the long-range repulsion upon the velocity profile are examined in conjunction with the friction factor. It is evident that the fluid slip counteracts the effect by the electric double layer and induces a larger flow rate. Particle streak imaging by fluorescent microscope and the data processing method developed ourselves are applied to straight channel designed to allow for flow visualization of dilute latex colloids underlying the condition of simple fluid. The reliability of the velocity profile determined by the flow imaging is justified by comparing with the finite difference solution. We recognized the behavior of fluid slip in velocity profiles at the hydrophobic surface of polydimethylsiloxane wall, from which the slip length was evaluated for different conditions.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.41-45
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• 2018

As the size of semiconductor chip shrinks, the electronic industry has been paying close attention to fan-out wafer level packaging (FO-WLP) as an emerging solution to accommodate high input and output density. FO-WLP also has several advantages, such as thin thickness and good thermal resistance, compared to conventional packaging technologies. However, one major challenge in current FO-WLP manufacturing process is to control wafer warpage, caused by the difference of coefficient of thermal expansion and Young's modulus among the materials. Wafer warpage induces misalignment of chips and interconnects, which eventually reduces product quality and reliability in high volume manufacturing. In order to control wafer warpage, it is necessary to understand the effect of material properties and design parameters, such as chip size, chip to mold ratio, and carrier thickness, during packaging processes. This paper focuses on the effects of thickness of chip and molding compound on 12" wafer warpage after PMC of EMC using finite element analysis. As a result, the largest warpage was observed at specific thickness ratio of chip and EMC.

• Journal of Sensor Science and Technology
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• v.29 no.2
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• pp.128-132
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• 2020

Total organic carbon (TOC) analysis equipment, which was previously used to prevent eutrophication in advance, is heavy, bulky, and expensive; therefore, so it is difficult to be carried and has been used as an experimental unit. In this study, a through-carbon analysis chip that integrates pretreatment through photocatalytic oxidation and carbon dioxide measurement using a pH indicator was investigated. Both the total carbon - inorganic carbon method and the nonpurgeable organic carbon (NPOC) measurement method require an acidification part for injecting an acid solution for inorganic carbon measurement and removal, an oxidation part for total carbon or NPOC oxidation and a measurement part for Carbon dioxide (CO₂) measurement. Among them, the measurement of oxidation and CO₂ requires physical technology. The proposed TOC analysis chip decomposed into CO₂ as a result of the oxidizing of organic carbon using a photocatalyst, and the pH indicator that was changed by the generated CO₂ was optically measured. Although the area of the sample of the oxidation part and the pH indicator of the measurement part were distinguished in an enclosed space, CO₂ was quantified by producing an oxidation part and a measurement part that shared the same air in one chip. The proposed TOC analysis chip is less expensive and smaller, cost and size are disadvantages of existing organic carbon analysis equipment, because it does not require a separate carrier gas to transport the CO₂ gas in the oxidation part to the measurement part.