• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1994-2000
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• 1993

A new lattice structure using decision feedback and augmented prediction for estimating and suppressing the narrowband interference is presented. The performance of the proposed interference canceller is compared to the conventional interference cancellation filter. The reference signal of the interference canceller is formed by using the chip decisions, which is correlated with the narrowband interference components of the received signal. The decision feedback technique reduce the distortion of the desired signal which is introduced by the interference canceller through the use of feedback chip decisions. And by linear prediction of the error signal, the residual interference component of can be eliminated, Using this unconteminated error signal to update the adaptive filter coefficients, the performance of the rejection can be improved. In the simulation, it is assumed that the processing gains are 7 and 15, signal to interference ratio is -10[dB], and 5% interference band. The results show that the BER performance of the proposed filter structure is improved by 1~3dB.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.5
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• pp.331-337
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• 2014

Ge is becoming an increasingly popular semiconductor material with high Si compatibility for on-chip optical interconnect technology. For a better manifestation of the meritorious material properties of Ge, its surface treatment should be performed satisfactorily before the electronic and photonic components are fabricated. Ex-situ rapid thermal annealing (RTA) processes with different gases were carried out to examine the effects of the annealing gases on the thin-film quality of Ge grown epitaxially on Si substrates. The Ge-on-Si samples were prepared in different structures using the same equipment, reduced-pressure chemical vapor deposition (RPCVD), and the samples annealed in $N_2$, forming gas (FG), and $O_2$ were compared with the unannealed (deposited and only cleaned) samples to confirm the improvements in Ge quality. To evaluate the thin-film quality, room-temperature photoluminescence (PL) measurements were performed. Among the compared samples, the $O_2$-annealed samples showed the strongest PL signals, regardless of the sample structures, which shows that ex-situ RTA in the $O_2$ environment would be an effective technique for the surface treatment of Ge in fabricating Ge devices for optical computing systems.

• Smart Media Journal
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• v.1 no.1
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• pp.1-9
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• 2012

This Paper proposes an effective SoC hardware architecture implementing a VDP for Full HD TVs. The proposed architecture makes real time video processing possible with supporting efficient bus architecture and flexible interface. Video IP cores in the VDP are designed to provide a high quality of improved image enhancement function. The Avalon interface is adopted to guarantee real-time capability to IPs as well as SoC integration. This leads to reduced design time and also enhanced designer's convenience due to the easiness in IP addition, deletion, and revision for IP verification and SoC integration. The embedded software makes it possible to implement flexible real-time system by controlling setting parameter details and data transmitting schemes in real-time. The proposed VDP SoC design is implemented on Cyclon III SoPC platform. The experimental results show that our proposed architecture of the VDP SoC successfully provides required quality of Video image by converting SD level input to Full HD level image.

• Journal of the Korean Association of Geographic Information Studies
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• v.8 no.4
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• pp.14-23
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• 2005

This paper proposes a method for matching two different images, especially satellite images. In the general image matching fields, when an image is compared to other image, they may have different properties on the size, contents, brightness, etc. If there is no noise in each image, in other words, they have identical pixel level and unchanged edges, the image matching method will be simple comparison between two images with pixel by pixel. However, in many applications, most of images to be matched should have much different properties. This paper proposes an efficient method for matching satellite images. This method is to match a raw satellite image with GCP chips. From this we can make a geometrically corrected image. The proposed method is based on wavelet transformation, not required any pre-processing such as histogram equalization, analysis of raw image like the traditional methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.42-50
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• 2006

Owing to the development of semiconductor processing technology, high density complex circuits can be integrated in a System-on-Chip (SoC). However, increasing energy consumption becomes one of the most important limiting factors. Power estimation at the early stage of design is essential, since design changes at lower levels may significantly lengthen the design period and increase the cost. In this paper, logic level circuits ire levelized and several levels are selected to build power model tables for efficient power estimation. The proposed techniques are applied to a set of ISCAS'85 benchmark circuits to illustrate their effectiveness. Experimental results show that significant improvement in estimation accuracy and slight improvement in efficiency are achieved when compared to those of a well-known existing method. The average estimation error has been reduced from $9.49\%\;to\;3.84\%$.

• Journal of Biosystems Engineering
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• v.26 no.2
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• pp.163-168
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• 2001

A manipulator for test-cup attachment modules, which was a part of a robot milking system, was developed to reduce cost and labor for cow milking processing. A Cartesian coordinate manipulator was designed for the milking process, because it was quite flexible and can be constructed more economically than any other configuration. The manipulator was made use of DC motors, screws for power transmission, a RS422 interface system for the transmission of coordinate values and a one-chip microprocessor, 89C52. Performance tests of the manipulator were conducted to measure experimentally the precision of all axes. Some of the results are as follows. 1. The Cartesian coordinate manipulator was designed and built. Dimension of the three perpendicular axes (X, Y, and Z) and one arm’s axis(W) to pick up and transfer the modules were 700㎜$\times$450㎜$\times$550㎜$\times$650㎜. The arm’s axis moved the teat-cup attachment module, which attached four teat-cup to four teats, detached four teat-cup from four teats, was designed and manufactured by using CAD, CAM and CNC. 3. After 10 replications of exercising the manipulator, mean precision values(positioning error) of X, Y, Z axes wee 0.48㎜, 0.20㎜, 0.19㎜, respectively. Therefore, we conclude the axes to have a precision better than 0.5㎜, had no problem to operate correctly the milking manipulator.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.149-159
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• 2003

The need for information security increases interests on cipher algorithms recently. Especially, a large volume of data transmission over high-band communication network requires faster encryption and decryption techniques for real-time processing. It would be a good solution for this problem that we implement the cipher algorithm in forms of hardware circuits. Though some previous researches use this approach, they focus only on repeatedly executing the core part of the algorithm to minimize the hardware chip size, while most cipher algorithms are inherently parallel. In this paper, we propose a new design for the SEED block cipher algorithm developed by KISA (Korea Information Security Agency) in 1998 as Korean standard cipher algorithm. It exploits the parallelism of the algorithm basically and implements it in a pipelined fashion. We described the design in VHDL program and performed functional simulations on the program, and then found that it worked correctly. In addition, we synthesized it and verified that it could be implemented in a single FPGA chip, implying that the new design can be Practically used for the actual hardware implementation of a high-speed and high-performance cipher system.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.26-36
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• 1999

In this paper, the novel scheme of OAM performance management function is proposed to supply the most of network resources and reliable services by processing data having various QoS(quality of service) in the view of cell loss and cell delay of ATM networks Also, the special fields of OAM cell are defined in order to improve correlate control, operation, and management technique between networks which is required to flexibility and precision control as detecting the performance information of the variable networks periodically. The proposed OAM function, the input/output function of cell, and the interface function of the accessory device which is likely to the memory/CPU are designed to ASIC. The designed chip is carried out the back-end simulation using Verilog-XL simulator of Cadence. In result, it is able to performs an accurate control in $2{\mu}s$.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.8
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• pp.12-19
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• 2017

In this paper a super-resolution time delay estimation algorithm that estimates the time delays of spread spectrum signals using sparse signal reconstruction approach is introduced. So far, the correlation method has been mostly used to estimate the time delays of spread spectrum signals. However it fails to accurately estimate the time delays in the case where the signals are spaced within approximately 1 PN chip duration and a further processing should be applied to the correlation outputs in order to enhance the resolution capability. Recently sparse signal approaches attract much interest in the area of directions-of-arrival estimation, of which SPICE is the most representative. Thus we introduce a super-resolution time delay estimation algorithm based on the SPICE approach and compare its performance with that of MUSIC algorithm by applying them to the ISO/IEC 24730-2.1 RTLS system.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.34-41
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• 1998

An integrated circuit for magnetic stripe storage system is implemented. All the analog and digital circuits are integrated in one chip. The analog block contains preamplifier, peak detecter, comparator and reference generater. And digital block includes reference window signal generater, up/down counter for F/2F signal measurement, bit-error detection logic, and control logic. Both the encoding and decoding functions for F/2F signal processing are provided. An AGC(automatic gain control) circuit which was included in conventional circuits is eliminated due to optimized circuit design. Misreading prevention circuits are also proposed by fixing up new reference bit when broken bits are detected. The prototype chip is implemented using $0.8{\mu}m$ N-well CMOS technology and operates from 3.3 V to 7.5 V of supply voltage. It occupies a die area of $3.04mm^2(1.6mm{\times}1.9mm)$ and dissipates 8 mW with a 5 V supply voltage.