• Journal of Advanced Marine Engineering and Technology
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• v.35 no.7
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• pp.930-937
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• 2011

The characteristics of mean velocity and turbulence have been analyzed in the circular open channel flow using PIV measurement data for a wide range of water depth. The measured data are fitted to a velocity distribution function over the whole depth of the open channel. Reynolds shear stress and mean velocity in wall unit are compared with the analytic models for fully-developed turbulent boundary layer. Both the mean velocity and Reynolds shear stress have different distributions from the two-dimensional boundary layer flow when the water depth increases over 50% since the influence of the side wall penetrates more deeply into the free surface. The cross-stream Reynolds normal stress also has considerably different distribution in view of its peak value and decreasing rate in the outer region whether the water depth is higher than 50% or not.

• Journal of Mechanical Science and Technology
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• v.16 no.11
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• pp.1522-1539
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• 2002

In the present study, an explicit algebraic stress model is shown to be the exact tensor representation of algebraic stress model by directly solving a set of algebraic equations without resort to tensor representation theory. This repeals the constraints on the Reynolds stress, which are based on the principle of material frame indifference and positive semi-definiteness. An a priori test of the explicit algebraic stress model is carried out by using the DNS database for a fully developed channel flow at Rer = 135. It is confirmed that two-point correlation function between the velocity fluctuation and the Laplacians of the pressure-gradient i s anisotropic and asymmetric in the wall-normal direction. Thus, a novel composite algebraic Reynolds stress model is proposed and applied to the channel flow calculation, which incorporates non-local effect in the algebraic framework to predict near-wall behavior correctly.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.485-488
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• 2004

As scaling down the cell channel length, the increment of B concentration in channel region is inevitable to overcome the punch-through, especially in flash memory cell with 90nm technology. This paper shows that the high dose ion implantation in channel cause the Si defect. which has been proved to be the major cause of the tailed Vth in distribution. And also mechanical stress due to SiN-anneal process can induce the Si dislocation. and get worse it. With decreasing the channel implantation dose, skipping the anneal and reducing the mechanical stress, Si defect problem is solved completely. We are verify first that the optimization of B concentration in channel must be certainly considered in order to improve Si defect. It is also certainly necessary to stabilize the distribution of cell Vth in the next generation of flash memory.

• Structural Engineering and Mechanics
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• v.74 no.3
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• pp.445-455
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• 2020

Shear lag phenomenon has long been taken into consideration in various structural codes; however, the AISC provisions have not proposed any specific equation to calculate the shear lag ratio in some cases such as fillet-welded connections of front-to-front double channel sections. Moreover, those equations and formulas proposed by structural codes are based on the studies that were conducted on riveted and bolted connections, and can be applied to single channel sections whilst using them for fillet-welded double channels would be extremely conservative due to the symmetrical shape and the fact that bending moments will not develop in the gusset plate, resulting in less stress concentration. Numerical models are used in the present study to focus on parametric investigation of the shear lag effect on fillet-welded tension connection of double channel section to a gusset plate. The connection length, the eccentricity of axial load, the free length and the thickness of gusset plate are considered as the key factors in this study. The results are then compared to the estimates driven from the AISC-LRFD provisions and alternative equations are proposed.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.199-200
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• 2006

It will not be an exaggeration to say that one of the most important features of RT (Rapid Tooling) technology is to easy manufacturing complex shape of cooling channel in injection mold. That is, RT technology is hardly influenced complex shape of tool, Therefore, mold designer can optimize the position and shape of cooling channel whatever they want. In this study, we optimized cooling channel through CAE analysis to solve the problem; prototype-connector-mold applied conventional cooling channel, locally warped by internal stress: The effect of three-dimensional cooling channel was supported by simulation result. But it is impossible to produce injection mold applied three-dimensional cooling channel through machining operation. Therefore, we produced the prototype-connector-mold with three-dimensional cooling channel using Direct Metal Laser Sintering (DMLS) process, and get good-quality prototype-connector without warpage.

• Journal of the Korean Society for Precision Engineering
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• v.25 no.11
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• pp.100-106
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• 2008

We have studied the characteristic changes of optical device using imprint lithography. An imprinted structure is inherently involved in residual stress due to the temperature and the pressure cycle during fabrication process. A structure with residual stress undergoes stress relaxation, which leads io dimensional change. Therefore, annealing processes was performed to reduce the residual stress of imprinted polymer channel. Reduction of residual stress was confirmed through dimensional change, birefringence, and the mechanical properties. We have fabricated an optical device, and it saw the optical intensity changes within 0.1% for 1 month.

• Journal of the Korean Society of Safety
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• v.19 no.3 s.67
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• pp.78-83
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• 2004

The channel-type lining board that partial welded on many partition frames is used to normal servicing lining board type. On this study is to investigate existing channel-type lining board's capacity by using the static loading test. From this study, to develop new-type lining board which reflect well cross section area and sectional modulus of existing channel-type lining board. Six types FEM model are adopted. The accumulated test results of stress conditions and deflections by section shapes will be used to analyzed the relation between the capacity and the section shape. With the comparing the results of static loading test and FEM analysis.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1047-1050
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• 2009

The two approaches to improve the stability of oxide TFTs are described. First approach is the optimization of device architecture including MIS structure and passivation layer using conventional InGaZnO semiconductor channel layer. Second approach is to develop the new kinds of oxide semiconductor materials, which is very robust and stable against the gate bias stress and thermal stress.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.12
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• pp.792-796
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• 2014

In this paper, we investigated the hot carrier reliability of two kinds of device with low threshold voltage (LVT) and regular threshold voltage (RVT) in 65 nm CMOS technology. Contrary to the previous report that devices beyond $0.18{\mu}m$ CMOS technology is dominated by channel hot carrier(CHC) stress rather than drain avalanche hot carrier(DAHC) stress, both of LVT and RVT devices showed that their degradation is dominated by DAHC stress. It is also shown that in case of LVT devices, contribution of interface trap generation to the device degradation is greater under DAHC stress than CHC stress, while there is little difference for RVT devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.94-100
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• 2017

Stress drain bias dependent current model is proposed for sub-70-nm p-channel metal-oxide semiconductor field-effect transistors (pMOSFETs) under drain-avalanche-hot-carrier (DAHC-) mechanism. The proposed model describes the both on-current and off-current degradation by using two device parameters: channel length variation (${\Delta}L_{ch}$) and threshold voltage shift (${\Delta}V_{th}$). Also, it is a simple and effective model of predicting reliable circuit operation and standby power consumption.