• Title/Summary/Keyword: channel resistance

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Effect of P-Base Region on the Transient Characteristics of 4H-SiC DMOSFETs (P형 우물 영역에 따른 4H-SiC DMOSFETs의 스위칭 특성 분석)

  • Kang, Min-Seok;Ahn, Jung-Jun;Sung, Bum-Sik;Jung, Ji-Hwan;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.352-352
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    • 2010
  • Silicon Carbide (SiC) power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. In this paper, we report the effect of the P-base doping concentration ($N_{PBASE}$) on the transient characteristics of 4H-SiC DMOSFETs. By reducing $N_{PBASE}$, switching time also decreases, primarily due to the lowered channel resistance. It is found that improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the and channel resistance. Therefore, accurate modeling of the operating conditions are essential for the optimization of superior switching performance.

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A Study on the Principal Performance of Purse Seiner Ship in 2 Vessels Formation (2척 선단 선망본선의 주요성능에 관한 연구)

  • 최낙경;강병윤;조효제
    • Journal of Ocean Engineering and Technology
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    • v.16 no.6
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    • pp.71-75
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    • 2002
  • In this paper, a study on the principal performance of the purse seiner ship in two vessel formations was conducted. For this task, the outline of the purse seiner fishing system in two vessel formations was reviewed. At the same time, based on the general arrangement plan, hull from of the main vessel was developed. And the stability and ship motion characteristics of the ship design were estimated. Finally, to verify the characteristics of the resistance and self-propulsion coefficient, a model test in a circulating water channel was performed. As n result, it is anticipated that this presentation will be used as the foundation material for research of purse seiner.

Large-Signal Output Equivalent Circuit Modeling for RF MOSFET IC Simulation

  • Hong, Seoyoung;Lee, Seonghearn
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.5
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    • pp.485-489
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    • 2015
  • An accurate large-signal BSIM4 macro model including new empirical bias-dependent equations of the drain-source capacitance and channel resistance constructed from bias-dependent data extracted from S-parameters of RF MOSFETs is developed to reduce $S_{22}$-parameter error of a conventional BSIM4 model. Its accuracy is validated by finding the much better agreement up to 40 GHz between the measured and modeled $S_{22}$-parameter than the conventional one in the wide bias range.

A study on the hull form development of the G/T 340ton class high speed fishery patrol ship (G/T 340톤급 고속 어업지도선의 선형개발에 관한 연구)

  • 이귀주;이광일
    • Journal of Ocean Engineering and Technology
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    • v.11 no.4
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    • pp.221-226
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    • 1997
  • This study was carried out for the hull form development of G/T 340ton class high speed fishery patrol ship by Chosun University at the Circulating Water Channel cooperatively with Korea Maritime Service. Same size of 15knots class fishery patrol ship was selected as a parent form (Model number : CU-015), and modified fore and after body to be suitable for the operation at 20 knots. To minimize the breaking wave in the vicinity of fore body at high speed zone, high bulb nose and slender fore body hull form was chosen as an initial condition. Meanwhile, to ensure the engine room space keeping high resistance-propulsion performance, U-type stern hull form was developed.

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Analysis for Series Resistance of Amorphous Silicon Thin Film Transistor (비정질 실리코 박막 트랜지스터의 직렬 저항에 관한 분석)

  • Kim, Youn-Sang;Lee, Seong-Kyu;Han, Min-Koo
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.43 no.6
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    • pp.951-957
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    • 1994
  • We present a new model for the series resistance of inverted-staggered amorphous silicon (a-Si) thin film transistors (TFT's) by employing the current spreading under the source and the drain contacts as well as the space charge limited current model. The calculated results based on our model have been in good agreements with the measured data over a wide range of applied voltage, gate-to-source and gate-to-drain overlap length, channel length, and operating temperature. Our model shows that the contribution of the series resistances to the current-voltage (I-V) characteristics of the a-Si TFT in the linear regime is more significant at low drain and high gate voltages, for short channel and small overlap length, and at low operating temperature, which have been verified successfully by the experimental measurements.

An Exper imenta1 Study for Bow Hull Form Development of Catamaran Type Sweeping Vessel (쌍동형 부유쓰레기 청소선의 선수선형 개량을 위한 실험적 연구)

  • 정우철;박찬원;홍기섭;유호근
    • Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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    • 2001.05a
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    • pp.53-59
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    • 2001
  • In this Paper, the resistance performances of twin hull forms, which are simplified as two-dimensional wedge shape, are experimentally investigated in low and middle speed ranges to find out the effect of distance between two hulls and fore-body shape for the future hull form development of catamaran type sweeping vessel. The model tests are performed for seven different cases for three models in the circulating water channel(CWC) of Inha Technical College. The free surface flows are observed together to investigate the relation between resistance performance and free surface characteristics. A conceptual design for the modification of bow hull form is presented and the efficiency is discussed.

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The Analysis of I-V characteristics on n-channel offset gated poly-Si TFT`s (Offset 구조를 갖는 n-채널 다결정 실리콘 박막 트랜지스터의 I-V 분석)

  • 변문기;이제혁;김동진;조동희;김영호
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.05a
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    • pp.26-29
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    • 1999
  • The I-V characteristics of the n-channel offset gated poly-Si TETs have been systematically investigated in order to analyse the effects of offset region. The on currents are reduced due to the series resistance by the offset length and there is no kink phenomenon in offset devices. The off currents of the offset gated TFTs are remarkably reduced to 10$^{-12}$ A independent of gate and drain voltage because the electric field is weakened by the increase of the depletion region width near the drain region. It is shown that the offset regions behave as a series resistance and reduce lateral and vertical electric field.

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Initial Hull Form Development of Small-Size Coastal Leisure Boat (연안용 소형 레저선박의 초기선형 개발)

  • Jeong, Uh-Cheul;Park, Je-Woong;Koo, Jong-Do;Kim, Do-Jung
    • Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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    • 2003.05a
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    • pp.192-197
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    • 2003
  • Initial hull form of 3 G/T and $20{\sim}25$ knots class coastal leisure boat is newly developed. The performances, which are resistance, trim and sinkage, are investigated at high speed circulating water channel (CWC). Wave patterns are observed together to make clear the relation between the resistance performance and the wave characteristics.

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The effect of inlet air temperature for the cooling of the military electronic chip on the thermal conductive board (공기온도가 열전도성 기판 위에 탑재된 군용 전자칩 냉각에 미치는 영향)

  • 이진호
    • Journal of the Korea Institute of Military Science and Technology
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    • v.5 no.2
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    • pp.195-206
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    • 2002
  • The conjugate heat transfer from the simulated module in a horizontal channel with the variation of inlet air temperature is experimentally investigated. The aim of this study is to estimate temperature difference between a module and inlet air. This study is performed with the variation of parameters that are inlet air temperature(Ti=25~$55^{\circ}C), thermal resistance( $R_c$=0.05, 4.11, 158 K/W), inlet air velocity(Vi=0.1~1.5m/s), and input power(Q=3, 7 W). The results show that the effect of inlet air temperature is little, at the case of using conductive board. And input power was most effective parameter on the temperature difference between module and Inlet air.

Electrical Characteristics of High-Voltage LDMOSFET Fabricated by CMOS Technology (CMOS 공정으로 구현한 고전압 LDMOSFET의 전기적 특성)

  • Park, Hoon-Soo;Lee, Young-Ki;Kwon, Young-Kyu
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.07a
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    • pp.201-202
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    • 2005
  • The electrical characteristics of high-voltage LDMOSFET (Lateral Double-diffused MOSFET) fabricated by a CMOS technology were investigated depending on the process and design parameters. The off-state breakdown voltages of n-channel LDMOSFETs were linearly increased with increasing to the drift region length. For the case of decreasing n-well ion implant doses from $1.0\times10^{13}/cm^2$ to $1.0\times10^{12}/cm^2$, the off-state breakdown voltage was increased approximately two times, however, the on-resistance was also increased about 76%. Moreover, the on- and off-state breakdown voltages were also linearly increased with increasing the channel to n-tub spacing due to the reduction of impact ionization at the drift region.

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