• Journal of Advanced Marine Engineering and Technology
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• v.30 no.2
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• pp.231-238
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• 2006

The performance of free-breathing polymer electrolyte membrane fuel cell (PEMFC) was studied experimentally and the effect of cathode separator structure on the cell performance was investigated. Cathode separators were used for the cell with $18cm^2$ active area. In channel type, the contact resistance is low, and the nature convection. which is strongly affected by the cross-sectional shape of cathode separator channel, is dominant in a cell performance. The maximum power density with $18cm^2$ active area is $105mW/cm^2$ using the 10mm depth and 2mm width channel. A computational analysis was optimum structure of free-breathing channel type PEMFC for robotic application.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.210-214
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• 2016

In this paper, the decrease in the contact resistance of Ni germanide/Ge contact was studied as a function of the thickness of the antimony (Sb) interlayer for high performance Ge MOSFETs. Sb layers with various thickness of 2, 5, 8 and 12 nm were deposited by RF-Magnetron sputter on n-type Ge on Si wafers, followed by in situ deposition of 15nm-thick Ni film. The contact resistance of samples with the Sb interlayer was lower than that of the reference sample without the Sb interlayer. We found that the Sb interlayer can lower the contact resistance of Ni germanide/Ge contact but the reduction of contact resistance becomes saturated as the Sb interlayer thickness increases. The proposed method is useful for high performance n-channel Ge MOSFETs.

• Journal of Korea Water Resources Association
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• v.52 no.4
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• pp.255-264
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• 2019

The trapezoidal ribs had been installed in the retaining wall in order to reduce to flood damage in the impingement of mountain rivers. In this study, experiments in open channel with the trapezoidal ribs on sidewall were conducted to evaluate the effect of flow resistance by the trapezoidal shape. The hydraulic flow characteristics according to the flow rates were surveyed where the wall roughness is k-type that dimensionless spacings, ${\lambda}_{nv}$, are 6, 9, and 12. The flow-resistance factors such as roughness and friction coefficients increased generally with increase of the spacing of ribs. In high flow rate the friction coefficient showed the maximum value when ${\lambda}_{nv}$ is 9. Though the trapezoidal ribs has the relatively smaller flow resistance compared to the square ribs, their form drag accounted for mean 62% of the total flow resistance. It was confirmed that the optimal spacing of trapezoidal ribs to maximize the effect of flow resistance as the wall roughness increases are 9 to 12 times of the height of trapezoidal ribs.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.83-87
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• 2023

In the field of electronics and semiconductor technology, innovative semiconductor material research to replace Si is actively ongoing. However, while research on alternative materials is underway, there is a significant lack of studies regarding the relationship between 2D materials used as channels in transistors, especially parasitic resistance, and RF (radio frequency) applications. This study systematically analyzes the impact on electrical performance with a focus on various transistor structures to address this gap. The research results confirm that access resistance and contact resistance act as major factors contributing to the degradation of semiconductor device performance, particularly when highly scaled down. As the demand for high-frequency RF components continues to grow, establishing guidelines for optimizing component structures and elements to achieve desired RF performance is crucial. This study aims to contribute to this goal by providing structural guidelines that can aid in the design and development of next-generation RF transistors using 2D materials as channels.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.26 no.7
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• pp.1022-1030
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• 2002

The experiments were performed with a $31{\times}31{\times}7mm^3$ simulated 3-dimensional module on the thermal conductive board of a parallel plate channel. The convective thermal conductance for the path from the module surface directly to airflow and conjugate thermal conductance for the path leading from the module to the floor by way of a module support, then, to the airflow were determined with several combinations of module-support-construction(210, 0.32, 0.021 K/W)/floor-material(398, 0.236W/mK) and channel height(15-30mm). As the result, it was found that the conjugate thermal conductance and the temperature distribution around the module depend on the thermal resistance of the module support, and the channel height. These configurations were designed to investigate on the feasibility of using the substrate as an effective heat spreader in the forced convective air-cooling of surface mounted heat source. The experimental results were discussed in the light of interactive nature of heat transfer through two paths, one directed from the module to the airflow and the other via the module support and the floor to the air.

• Journal of Electrical Engineering and Technology
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• v.7 no.2
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• pp.236-239
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• 2012

In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the $SiO_2$/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.131-131
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

• Proceedings of the KSME Conference
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• 2007.05b
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• pp.2432-2437
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• 2007

The demand of high speed and miniaturization of electronic devices results in increased power dissipation requirement for thermal management. In this work, the effects of microchannel width, height and liquid flowrate on the cooling performances of microchannel waterblock are investigated experimentally. The microchannel waterblock considered ranged in width from 0.5 to 0.9 mm, with the channel height being nominally 1.7 to 9 times the width in each case. The experiments were conducted using water, over a liquid flow rate ranging from 0.2 to 2.0 lpm. The base temperature, thermal resistance and pressure drop increase with increasing of liquid flow rate. The measured thermal resistances ranged from 0.10 to 0.23 $^{\circ}C$/W for the channel 5.

• Transactions on Electrical and Electronic Materials
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• v.17 no.3
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• pp.143-145
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• 2016

In order to find suitable source and drain (S/D) electrodes for amorphous InGaZnO thin film transistors (a-IGZO TFTs), the specific contact resistance of interface between the channel layers and various S/D electrodes, such as Ti/Au, a-IZO and multilayer of a-IGZO/Ag/a-IGZO, was investigated using the transmission line model. The a-IGZO TFTs with a-IGZO/Ag/a-IGZO of S/D electrodes had good performance and low contact resistance due to the homo-junction with channel layer. The stability was measured with different electrodes by a positive bias stress test. The result shows the a-IGZO TFTs with a-IGZO/Ag/a-IGZO electrodes were more stable than other devices.

• ETRI Journal
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• v.21 no.3
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• pp.22-28
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• 1999

A new tapered TEOS oxide technique has been developed to use field oxide of the power integrated circuits. It provides better uniformity of less than 3 % and reproducibility. On-resistance of P-channel RESURE (REduced SURface Field) LDMOS transistors has been optimized and improved by using a novel simulation and tapered TEOS field oxide on the drift region of the devices. With the similar breakdown voltage, at $V_{gs}$=-0.5V, the specific on-resistance of the LDMOS with the tapered field oxide is about $31.5{\Omega}{\cdot}cm^2$, while that of the LDMOS with the conventional field oxide is about $57m{\Omega}{\cdot}cm^2$.