• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.240-250
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• 2010

Double Gate MOSFETs (DG MOSFETs) with doping in one or two thin layers of an otherwise intrinsic channel are simulated to obtain the transport characteristics, threshold voltage and leakage current. Two different device structures- one with doping on two layers near the top and bottom oxide layers and another with doping on a single layer at the centre- are simulated and the variation of device parameters with a change in doping concentration and doping layer thickness is studied. It is observed that an n-doped layer in the channel reduces the threshold voltage and increases the drive current, when compared with a device of undoped channel. The reduction in the threshold voltage and increase in the drain current are found to increase with the thickness and the level of doping of the layer. The leakage current is larger than that of an undoped channel, but less than that of a uniformly doped channel. For a channel with p-doped layer, the threshold voltage increases with the level of doping and the thickness of the layer, accompanied with a reduction in drain current. The devices with doped middle layers and doped gate layers show almost identical behavior, apart from the slight difference in the drive current. The doping level and the thickness of the layers can be used as a tool to adjust the threshold voltage of the device indicating the possibility of easy fabrication of ICs having FETs of different threshold voltages, and the rest of the channel, being intrinsic having high mobility, serves to maintain high drive current in comparison with a fully doped channel.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.12
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• pp.69-75
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• 1997

A Si-channle MESFET using .delta.-doped layers was designed and the considerable enhancement of the current driving capability of the device was observed by simulation. The channel consists of double .delta.-doped layers separated by a low-doped spacer. Cariers are spilt from the .delta.-doped layers and are accumulated in the spacer. The saturation current is enhanced by the contribution of the carriers in the spacer. Among the design parameters that affect the peformance of the device, the thickness of the spacer and the ratio of the doping concentrations of the two .delta.-doped layers were studied. The spacer thickenss of 300~500.angs. and the doping ratio of 3~4 were shown to be the optimized values. The saturation current was observed to be increased by 75% compared with a bulk-channel MESFET. The performances of transconductance, output resistance, and subthreshold swing were also enhanced.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.2
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• pp.188-195
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• 1988

The electronic states in implanted n-type silicon inversion layers have been calculated by solving Schrodinger and Poisson's equations self-consistently. The results show that implantation affects seriously energy levels, populations, and electron distribution of n-type silicon inversion layers. The calcualted channel charge is in excellent agreement with the experimental data reported elsewhere. This analysis is expected to provide powerful means to evaluate the performance of implanted n-channel MOSTs.

• International Journal of Computer Science & Network Security
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• v.21 no.3
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• pp.48-54
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• 2021

Security is an important issue for wireless communications and poses many challenges. Most security schemes have been applied to the upper layers of communications networks. Since in a typical wireless communication, transmission of data is over the air, third party receiver(s) may have easy access to the transmitted data. This work examines a new security technique at the physical layer for the sake of enhancing the protection of wireless communications against eavesdroppers. We examine the issue of secret communication through Rayleigh fading channel in the presence of an eavesdropper in which the transmitter knows the channel state information of both the main and eavesdropper channel. Then, we analyze the capacity of the main channel and eavesdropper channel we also analyze for the symbol error rate of the main channel, and the outage probability is obtained for the main transmission. This work elucidate that the proposed security technique can safely complement other Security approaches implemented in the upper layers of the communication network. Lastly, we implement the results in Mat lab

• Journal of IKEEE
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• v.26 no.3
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• pp.500-505
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• 2022

In this study, we designed oxide thin-film transistors (TFTs) with dual gate and tri layered split channels, and investigated the structural effect of the TFTs on the electrical characteristics. The dual gates played a key role in increasing the driving current, and the channel structure of tri layers and split form contributed to the increase in the carrier mobility. The tri layered channels consisting of the a-ITGZO and two ITO layers inserted between the gate dielectric and a-ITGZO led to the increase in the on-current by using ITO layers with high conductivity, and the split channels lowered series resistance of the channels. Compared with the mobility (15 cm²/V·s) of the single gate a-ITGZO TFT, the mobility (134 cm²/V·s) of the dual gate tri-layer split channel TFT was remarkably enhanced by the structural effect.

• ETRI Journal
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• v.27 no.4
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• pp.439-445
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• 2005

We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.541-544
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• 1998

A SiGe p-channel MESFET using $\delta-doped$ layers is designed and the considerable enhancement of the current driving capability of the device is observed from the result of simulation. The channel consists of double $\delta-doped$ layers separated by a low-doped spacer which consists of Si and SiGe. A quantum well is formed in the valence band of the Si/SiGe heterojunction and much more holes are accumulated in the SiGe spacer than those in the Si spacer. The saturation current is enhanced by the contribution of the holes inthe spacer. Among the design parameters that affect the performance of the device, the thickness of the SiGe layer and the Ge composition are studied. The thickness of $0~300\AA$ and the Ge composition of 0~30% are investigated, and the saturation current is observed to be increased by 45% compared with a double $\delta-doped$ Si p-channel MESFET.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.19 no.1
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• pp.114-120
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• 2020

In this study, the process of freezing around two consecutively arranged channel tubes used for evaporator heat exchange was numerically investigated. Numerical results confirmed that the vortex occurred between the front channel and the rear channel and also that the vortex occurred due to the rapid change of the channel at the rear of the rear channel. These vortices were found to play a role in reducing the ice layer to some extent by the growth of the ice layer at the front and rear of the channel tube. The freezing layer showed a tendency to gradually increase as it passed through the channel pipe. As the wall temperature in the channel pipe decreased, the thickness of the freezing layer increased. As the flow rate of water slowed, the thickness of the freezing layer became thicker. In particular, in the case of a slow flow rate of 0.03 m/s, the freezing layers of the front channel pipe and the rear channel pipe were connected to each other. The narrower the channel, the thinner the freezing layer was in both the front and rear channel tubes. It is found that these thin freezing layers are caused by the low thickness of the temperature boundary layer formed around the channel tube.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.99-99
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• 2010

Recently, amorphous transparent oxide semiconductors (TOS) have been widely studied for many optoelectronic devices such as AM-OLED (active-matrix organic light emitting diodes). The TOS TFTs using a-IGZO channel layers exhibit a high electron mobility, a smooth surface, a uniform deposition at a large area, a high optical transparency, a low-temperature fabrication. In spite of many advantages of the sputtering process such as better step coverage, good uniformity over large area, small shadow effect and good adhesion, there are not enough researches about characteristics of a-IGZO thin films. In this study, therefore, we focused on the electrical properties of a-IGZO thin films as a channel layer of TFTs. TFTs with the a-IGZO channel layers and Y2O3 gate insulators were fabricated. Source and drain layers were deposited using ITO target. TFTs were deposited on unheated non-alkali glass substrates ($5cm{\times}5cm$) with a sintered ceramic IGZO disc (3 inch $\varnothing$, 5mm t), Y2O3 disc (3 inch $\varnothing$, 5mm t) and ITO disc (3 inch $\varnothing$, 5mm t) as a target by magnetron sputtering method. The O2 gas was used as the reactive gas. Deposition was carried out under various sputtering conditions to investigate the effect of sputtering process on the characteristics of a-IGZO thin films. Correlation between sputtering factors and electronic properties of the film will be discussed in detail.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.11
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• pp.905-909
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• 2009

The new Junction Field Effect Transistors (JFETs) with Silicon-germanium (SiGe) layers is investigated. This structure uses SiGe layer to prevent out diffusion of boron in the channel region. In this paper, we report electrical properties of SiGe JFET measured under various design parameters influencing the performance of the device. Simulation results show that out diffusion of boron is reduced by the insertion SiGe layers. Because the SiGe layer acts as a barrier to prevent the spread of boron. This proposed JFET, regardless of changes in fabrication processes, accurate and stable cutoff voltage can be controlled. It is easy to maintain certain electrical characteristics to improve the yield of JFET devices.