• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.21-28
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• 1999

A new method of making high speed self-aligned ESD (Elevated Source/Drain) MOSFET is proposed. Different from the conventional LDD (Lightly-Doped Drain) structure, the proposed ESD structure needs only one ion implantation step for the source/drain junctions, and makes it possible to modify the depth of the recessed channel by use of dry etching process. This structure alleviates hot-carrier stress by use of removable nitride sidewall spacers. Furthermore, the inverted sidewall spacers are used as a self-aligning mask to solve the self-align problem. Simulation results show that the impact ionization rate ($I_{SUB}/I_{D}$) is reduced and DIBL (Drain Induced Barrier Lowering) characteristics are improved by proper design of the structure parameters such as channel depth and sidewall spacer width. In addition, the use of removable nitride sidewall spacers also enhances hot-carrier characteristics by reducing the peak lateral electric field in the channel.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.7-13
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• 1998

The VLSI devices of submicron level trend to have a lowering of reliability because of hot carriers by two dimensional influences which are caused by short channel effects and which are not generated in a long channel devices. In order to minimize the two dimensional influences, much research has been made into various types of source/drain structures. MOS typed tunnel transistor with Schottky barrier junctions at source/drain, which has the advantages in fabrication process, downsizing and response speed, has been proposed. The experimental device was fabricated with p type silicon, and manifested the transistor action, showing the unsaturated output characteristics and the high transconductance comparing with that in field effect mode. The results of trial indicate for better performance as follows; high doped channel layer to lower the driving voltage, high resistivity substrate to reduce the leakage current from the substrate to drain.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.760-765
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• 2007

In this paper, the threshold voltage roll-off and drain induced barrier lowering(DIBL) have been analyzed for nano structure double gate FinFET. The analytical current model has been developed, including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics were used to calculate thermionic omission current, and WKB(Wentzel- Kramers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off and DIBL are very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects, and this process has to be developed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.110.1-110.1
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• 2012

Recently, advances in ZnO based oxide semiconductor materials have accelerated the development of thin-film transistors (TFTs), which are the building blocks for active matrix flat-panel displays including liquid crystal displays (LCD) and organic light-emitting diodes (OLED). However, the electrical performances of oxide semiconductors are significantly affected by interactions with the ambient atmosphere. Jeong et al. reported that the channel of the IGZO-TFT is very sensitive to water vapor adsorption. Thus, water vapor passivation layers are necessary for long-term current stability in the operation of the oxide-based TFTs. In the present work, $Al_2O_3$ and $TiO_2$ thin films were deposited on poly ether sulfon (PES) and $SnO_x$-based TFTs by electron cyclotron resonance atomic layer deposition (ECR-ALD). And enhancing the WVTR (water vapor transmission rate) characteristics, barrier layer structure was modified to $Al_2O_3/TiO_2$ layered structure. For example, $Al_2O_3$, $TiO_2$ single layer, $Al_2O_3/TiO_2$ double layer and $Al_2O_3/TiO_2/Al_2O_3/TiO_2$ multilayer were studied for enhancement of water vapor barrier properties. After thin film water vapor barrier deposited on PES substrate and $SnO_x$-based TFT, thin film permeation characteristics were three orders of magnitude smaller than that without water vapor barrier layer of PES substrate, stability of $SnO_x$-based TFT devices were significantly improved. Therefore, the results indicate that $Al_2O_3/TiO_2$ water vapor barrier layers are highly proper for use as a passivation layer in $SnO_x$-based TFT devices.

• Journal of the Korean Society of Safety
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• v.32 no.4
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• pp.34-39
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• 2017

Typical flow regime of overflow at barrier or weir constructed in mid and small streams becomes as the submerged flow during most flood events. One of major causes of barrier failure has been reported as the levee-scour near the conjuction node between barrier and levee. However, most related design guidelines in Korea have not mentioned about the protection of levee around barrier or weir in detail. Furthermore, most previous researches have focused on the flow characteristics of overflow around several types of weirs but they did not have considered the material properties of levee itself. In this study, local scour near barrier was investigated with different material properties of levee under the submerged overflow condition which is assumed to reenact a flood event. Based on results from Fritz et al. and Mavis et al., a theoretical formula was also proposed in initial stage of laboratory experiments. And hydraulic experiments were carried out for the verification of the proposed formula. Levee was installed in the prismetic trapezoidal open channel and most parts were made of concrete except for movable section in which scour was expected to occur for the efficiency of experimental procedure. Each compaction of movable section in levee was followed by the basis of the KS F 2312. Further, after performing the experiments to find the optimum water content for each sediment, the specific amount of water was injected before flowing water. The difference between the proposed theoretical formula and experiment results was not much but considerable, which might be caused by the effect of compaction. For theoretical approach, it seemed that the formula did not take into account the compaction of levee, thus the correction coefficient for levee compaction determined in the literature was considered. Finally, the formula for the length of scour around barrier or weir was proposed, which can be useful to predict a levee in the reference design of revetment in mid and small streams. As shortly future study, scour length of levee around barrier or weir under different flow conditions such as perfect overflow condition will be studied and it will be able to contribute to suggest the design formula or criteria under all overflow conditions near barrier or weir.

• Journal of the Korean Geographical Society
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• v.40 no.4 s.109
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• pp.416-427
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• 2005

This paper aims to investigate morphological changes of deltaic barrier islands in the Nakdong Estuary and especially their spatial variations after barrage construction. We analyzed shorelines, geometrical centroids, and areas to reveal the changes of barrier islands. Here, we suggest three interesting points from this study. First, each individual barrier island in the Nakdong estuary goes through a different stage of the geomorphic cycle. The frontal barrier islands such as Sinja-do and Doyo-deung grow because they are located in front of the gates of the barrage. Sediments in water out of the gates are moved to offshore and then reworked by coastal processes such as waves and tides. Second, on the contrary, Baekhap-deung located behind Doyo-deung now diminishes indicating that sediments mainly move to the frontal growing island. Third, there is no morphological change in several barrier islands far away from the main flow of the Nakdong river such as Jinwoo-do, Daema-deung, and Jangja-do. In conclusion, barrier islands in the Nakdong estuary show distinct spatial variations. As a barrier island is closer to the main channel or is in the frontal location, there happens a very dynamic change in the morphology of the island.

• Reproductive and Developmental Biology
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• v.34 no.3
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• pp.153-159
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• 2010

The 34 potently pig pheromonal odorants (1-32, 5755 & 7113) through structure-based virtual screening and ligand-based virtual screening method were selected and their ADMET and pharmacokinetics characters were evaluated and discussed quantitatively. The pheromonal odorants were projected on the following pre-calculated models, Caco-2 cell permeability, blood-brain barrier permeation, hERG inhibition and volume-distribution. From the results of in silico study, it is found that an optimal compound (31) either penetrating or have a little ($P_{caco2}$=-8.143) for Caco-2 cell permeability, moderate penetrating ability ($P_{BBB}$=0.082) for blood-brain barrier permeation, the low QT prolongation ($P_{hERG}$=1.137) for the hERG $K^+$ channel inhibition, and low distribution into tissues ($P_{VD}$=-5.468) for volume-distribution. Therefore, it is predicted that the compound (31) a topical application may be preferable from these based foundings.

• Journal of the Korean Society of Safety
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• v.17 no.3
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• pp.112-117
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• 2002

A comparative investigation of an experimental and a simulation of chemical kinetics for NOx removal from silent(dielectric-barrier) discharges is presented. Several types of dielectric-barrier discharges were implemented depending upon the configuration of electrodes. The simulation was based on an approximate mathematical model for plasma cleaning of waste gas. The influence of non-uniform distributions of species due to the production of primary active particles in the streamer channel was taken into account. A comparison of observed experimental to the calculated removal efficiency of NOx showed acceptable agreement.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.80-81
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• 2008

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than $10^5$. Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.