• 제목/요약/키워드: cell transistor

검색결과 171건 처리시간 0.025초

High-Current Trench Gate DMOSFET Incorporating Current Sensing FET for Motor Driver Applications

  • Kim, Sang-Gi;Won, Jong-Il;Koo, Jin-Gun;Yang, Yil-Suk;Park, Jong-Moon;Park, Hoon-Soo;Chai, Sang-Hoon
    • Transactions on Electrical and Electronic Materials
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    • 제17권5호
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    • pp.302-305
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    • 2016
  • In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

500 V 급 Planar Power MOSFET의 P 베이스 농도 변화에 따른 설계 및 특성 향상에 관한 연구 (A Study About Design and Characteristic Improvement According to P-base Concentration Charge of 500 V Planar Power MOSFET)

  • 김권제;강예환;권영수
    • 한국전기전자재료학회논문지
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    • 제26권4호
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    • pp.284-288
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    • 2013
  • Power MOSFETs(Metal Oxide Semiconductor Field Effect Transistor) operate as energy control semiconductor switches. In order to reduce energy loss of the device during switch-on state, it is essential to increase its conductance. We have experimental results and explanations on the doping profile dependence of the electrical behavior of the vertical MOSFET. The device is fabricated as $8.25{\mu}m$ cell pitch and $4.25{\mu}m$ gate width. The performances of device with various p base doping concentration are compared at Vth from 1.77 V to 4.13 V. Also the effect of the cell structure on the on-resistance and breakdown voltage of the device are analyzed. The simulation results suggest that the device optimized for various applications can be further optimized at power device.

Partially-insulated MOSFET (PiFET) and Its Application to DRAM Cell Transistor

  • Oh, Chang-Woo;Kim, Sung-Hwan;Yeo, Kyoung-Hwan;Kim, Sung-Min;Kim, Min-Sang;Choe, Jeong-Dong;Kim, Dong-Won;Park, Dong-Gun
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제6권1호
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    • pp.30-37
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    • 2006
  • In this article, we evaluated the structural merits and the validity of a partially insulated MOSFET (PiFET) through the fabrication of prototype transistors and an 80 nm 512M DDR DRAM with partially-insulated cell array transistors (PiCATs). The PiFETs showed the outstanding short channel effect immunity and off-current characteristics over the conventional MOSFET, resulting from self-induced halo region, self-limiting SID shallow junction, and reduced junction area due to PiOX layer formation. The DRAM with PiCATs also showed excellent data retention time. Thus, the PiFET can be a promising alternative for ultimate scaling of planar MOSFET.

유속에 따른 열선의 과열비 조정을 통한 열선유속계의 감도향상에 관한 연구 (Sensitivity Enhancement of a Hot-Wire Anemometer by Changing Overheat Ratio with Velocity)

  • 이신표;고상근
    • 대한기계학회논문집
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    • 제19권10호
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    • pp.2678-2689
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    • 1995
  • In this study, a new hot-wire anemometer which has greater sensitivity than that of a constant temperature anemometer (CTA) was proposed. In contrast to CTA, the wire working resistance of the new anemometer increases with flow velocity, that is, the operating mode of the wire becomes variable temperature. The variable temperature anemometer(VTA) was made by substituting a voltage controlled variable resistor such as photoconductive cell or transistor for one of the resistors in the bridge. By positively feeding back the bridge top signal to the input side of these electronic components, the wire overheat ratio could be increased with velocity automatically. Static response analyses of the VTA, constant voltage anemometer (CVA) and CTA were made in detail and calibration experiments were performed to validate the proposed operating principle. The wire operating resistance of the CVA decreases with velocity and this leads to lower sensitivity than that of a CTA. But the sensitivity of the newly proposed VTA is superior to that of a CTA, since the wire overheat ratio increases with velocity. Consequently, it is found that the major factor that is responsible for large sensitivity of a VTA is not the working resistance itself but the change of the wire working resistance with velocity.

Interfacial Electronic Structures of Poly[N-9''-hepta-decanyl-2,7-carbazole-alt- 5,5-(4',7'-di-2-thienyl-2',1',3'-benzothiadiazole)] and [6,6]-phenyl C60 Butyric Acid Methyl Ester

  • Lee, Jung-Han;Seo, Jung-Hwa;Schlaf, Rudy;Kim, Kyoung-Joong;Yi, Yeon-Jin
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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    • pp.277-277
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    • 2012
  • PCDTBT (Poly[N-9''-hepta-decanyl-2,7-carbazole-alt-5,5-(4',7'-di-2-thienyl-2',1',3'-benzothiadiazole)]) is an attractive material as a semiconducting polymer for organic thin film transistor (OTFT) and organic solar cell (OSC). High power conversion efficiency (~6%) under simulated AM 1.5G solar illumination of bulk-heterojunction solar cell with PCDTBT and [6,6]-phenyl C60 butyric acid methyl ester (PC61BM) blend was reported. In OSC, it is known that the band alignment at the interface between donor and acceptor is critical. Therefore, we studied the interfacial electronic structures of PCDTBT and PC61BM. The polymers are deposited by electro-spray on gold and In-situ x-ray and ultraviolet photoelectron spectroscopy measurements revealed the interfacial electronic structures. We obtained the energy level alignment between two materials and the different interface formation was observed with different deposition order.

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A Novel PCCM Voltage-Fed Single-Stage Power Factor Correction Full-Bridge Battery Charger

  • Zhang, Taizhi;Lu, Zhipeng;Qian, Qinsong;Sun, Weifeng;Lu, Shengli
    • Journal of Power Electronics
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    • 제16권3호
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    • pp.872-882
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    • 2016
  • A novel pseudo-continuous conduction mode (PCCM) voltage-fed single-stage power factor correction (PFC) full-bridge battery charger is proposed in this paper. By connecting a freewheeling transistor in parallel with an input inductor, the PFC cell can operate in the PCCM with a constant duty ratio. Thus, the dc/dc stage can be designed using this constant duty ratio and the restriction on the duty ratio of the PFC cell is eliminated. As a result, the input current distortion is less and the dc bus voltage becomes controllable over the wide output power range of the battery charger. Moreover, the operation principle of the dc/dc stage is designed to be similar to that of a conventional phase-shifted full-bridge converter. Therefore, it is easy to implement. In this paper, the operation of the new converter is explained, and the design considerations of the controller and key parameters are presented. Simulation and experimental results obtained from a 1 kW prototype are given to confirm the operation of the proposed converter.

Electric Model of Li-Ion Polymer Battery for Motor Driving Circuit in Hybrid Electric Vehicle

  • Lee, June-Sang;Lee, Jae-Joong;Kim, Mi-Ro;Park, In-Jun;Kim, Jung-Gu;Lee, Ki-Sik;Nah, Wan-Soo
    • Journal of Electrical Engineering and Technology
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    • 제7권6호
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    • pp.932-939
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    • 2012
  • This paper presents an equivalent circuit model of a LIPB (Li-Ion Polymer battery) for Hybrid Electric Vehicles (HEVs). The proposed equivalent circuit can be used to predict the charging/discharging characteristics in time domain as well as the impedance characteristic analysis in frequency domain. Based on these features, a one-cell model is established as a function of Depth of Discharge (DoD), and a 48-cell model for a battery pack was also established. It was confirmed by experiment that the proposed model predict the discharging and impedance (AC) characteristics quite accurately at different constant current levels. To check the usefulness of the proposed circuit, the model was used to simulate a motor driving circuit with an Insulated Gate Bipolar Transistor (IGBT) inverter and Brushless DC (BLDC) motor, and it is confirmed that the model can calculate the battery voltage fluctuation in time domain at different DoDs.

인쇄전자 기술을 이용한 유기 태양전지 기술 개발 (Development of the Organic Solar Cell Technology using Printed Electronics)

  • 김정수;유종수;윤성만;조정대;김동수
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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    • pp.113.1-113.1
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    • 2011
  • PEMS (printed electro-mechanical system) is fabricated by means of various printing technologies. Passive and active compo-nents in 2D or 3D such as conducting lines, resistors, capacitors, inductors and TFT(Thin Film Transistor), which are printed withfunctional materials, can be classified in this category. And the issue of PEMS is applied to a R2R process in the manu-facturing process. In many electro-devices, the vacuum process is used as the manufacturing process. However, the vacuum process has a problem, it is difficult to apply to a continuous process such as a R2R(roll to roll) printing process. In this paper, we propose an ESD (electro static deposition) printing process has been used to apply an organic solar cell of thin film forming. ESD is a method of liquid atomization by electrical forces, an electrostatic atomizer sprays micro-drops from the solution injected into the capillary with electrostatic force generated by electric potential of about several tens kV. ESD method is usable in the thin film coating process of organic materials and continuous process as a R2R manufacturing process. Therefore, we experiment the thin films forming of PEDOT:PSS layer and active layer which consist of the P3HT:PCBM. The organic solar cell based on a P3HT/PCBM active layer and a PEDOT:PSS electron blocking layer prepared from ESD method shows solar-to-electrical conversion efficiency of 1.42% at AM 1.5G 1sun light illumination, while 1.86% efficiency is observed when the ESD deposition of P3HT/PCBM is performed on a spin-coated PEDOT:PSS layer.

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1.5-비트 비트 셀을 이용한 새로운 구조의 CMOS 전류모드 아날로그-디지털 변환기 (A New Architecture of CMOS Current-Mode Analog-to-Digital Converter Using a 1.5-Bit Bit Cell)

  • 최경진;이해길;나유찬;신홍규
    • 한국음향학회지
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    • 제18권2호
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    • pp.53-60
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    • 1999
  • 본 논문에서는 CSH(Current Sample-and-Hold)와 CCMP(Current Comparator)로 구성된 1.5-비트 비트 셀을 이용한 새로운 구조의 CMOS IADC(Current-mode Analog-to-Digital Convener)를 제안한다. 전체적인 IADC의 선형성 향상을 위하여 CFT(Clock Feedthrough)가 제거된 9-비트 해상도 CSH를 설계하여 각 비트 셀 전단에 배치하였다. 제안한 IADC를 구성하는 비트 셀은 2개의 래치 CCMP를 사용하기 때문에 디지털 교정 로직이 간소화되고 소비전력이 감소된다. 또한 IADC를 구성하는 모든 블록들의 회로는 MOS 트랜지스터로만 설계되었기 때문에 혼성모드 집적화에 유리하다. 제안한 IADC를 현대 0.8 ㎛ CMOS 파라미터로 HSPICE 시뮬레이션 결과, 20Ms/s에서 100 ㎑의 입력 신호에 대한 SNR은 43 dB로 7-비트의 해상도를 만족하였고 27 ㎽의 소비전력 특성을 나타냈다.

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PIII&D (Plasma immersion ion implantation & deposition)를 이용한 a-Ge (amorphous-Germanium) Thin Film의 결정성장

  • Jeon, Jun-Hong;Choi, Jin-Young;Park, Won-Woong;Lim, Sang-Ho;Han, Seung-Hee
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2011년도 제40회 동계학술대회 초록집
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    • pp.153-153
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    • 2011
  • 유리나 폴리머를 기판으로 하는 TFT(Thin film transistor), solar cell에서는 낮은 공정 온도에서($200{\sim}500^{\circ}C$) amorphous semiconductor thin film을 poly-crystal semiconductor thin film으로 결정화 시키는 기술이 매우 중요하게 대두 되고 있다. Ge은 Si에 비해 높은 carrier mobility와 낮은 녹는점을 가지므로, 비 저항이 낮을 뿐만 아니라 더 낮은 온도에서 결정화 할 수 있다. 하지만 일반적으로 쓰이는 Ge의 결정화 방법은 비교적 높은 열처리 온도를 필요로 하거나, 결정화된 원소에 남아있는 metal이 불순물 역할을 한다는 문제점, 그리고 불균일한 결정크기를 만든다는 단점이 있었다. 그 중에서도 현재 가장 많이 쓰이고 있는 MIC, MILC는 metal과 a-Ge이 접촉되는 interface나, grain boundary diffusion에 의해 핵 생성이 일어나고, 결정이 성장하는 메커니즘을 가지고 있으므로 단순 증착과 열처리 만으로는 앞서 말한 단점을 극복하는데 한계를 가지고 있다. 이에 PIII&D 장비를 이용하면, 이온 주입된 원소들이 모재와 반응 할 수 있는 표면적이 커짐으로 핵 생성을 조절 할 수 있을 뿐만 아니라, 이온 주입 시 발생하는 self annealing effect로 결정 크기까지도 조절할 수 있다. 또한 이러한 모든 process가 한 진공 장비 내에서 이루어지므로 장비의 단순화와, 공정간 단계별로 발생하는 불순물과 표면산화를 막을 수 있으므로 절연체 위에 저항이 낮고, hall mobility가 높은 poly-crystalline Ge thin film을 만들 수 있다. 본 연구에서는, 주로 핵 생성과정에서 seed를 만드는 이온주입 조건과, 결정 성장이 일어나는 증착 조건에 따라서 Ge의 결정방향과 크기가 많은 차이를 보이는데, 이는 HR-XRD(High resolution X-ray Diffractometer)와 Raman spectroscopy를 이용하여 측정 하였으며, SEM과 AFM으로 결정의 크기와 표면 거칠기를 측정하였다. 또한 Hall effect measurement를 통해 poly-crystalline thin film 의 저항과 hall mobility를 측정하였다.

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