• Journal of IKEEE
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• v.20 no.2
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• pp.163-166
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• 2016

It is important to operate the driving circuit under the optimal condition through precisely sensing the power consumption causing the temperature made mainly by the MOSFET (metal-oxide semiconductor field-effect transistor) when a BLDC (Brushless Direct Current) motor operates. In this letter, a Super-junction (SJ) power TMOSFET (trench metal-oxide semiconductor field-effect transistor) with an ultra-low specific on-resistance of $0.96m{\Omega}{\cdot}cm^2$ under the same break down voltage of 100 V is designed by using of the SILVACO TCAD 2D device simulator, Atlas, while the specific on-resistance of the traditional power MOSFET has tens of $m{\Omega}{\cdot}cm^2$, which makes the higher power consumption. The SPICE simulation for measuring the power distribution of 25 cells for a chip is carried out, in which a unit cell is a SJ Power TMOSFET with resistor arrays. In addition, the power consumption for each unit cell of SJ Power TMOSFET, considering the number, pattern and position of bonding, is computed and the power distribution for an ANSYS model is obtained, and the SJ Power TMOSFET is designed to make the power of the chip distributed uniformly to guarantee it's reliability.

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.130-134
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• 2008

The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.863-866
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• 2003

Recently, there has been growing interests in the magneto-resistive random access memory (MRAM) because of its great potential as a future nonvolatile memory. In this paper, a CMOS macro-model for MRAM cell based on a twin cell structure is proposed. The READ and WRITE operations of the MTJ cell can be emulated by adopting data latch and switch blocks. The behavior of the circuit is confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process. We expect the macro model can be utilized to develope the core architecture and the peripheral circuitry. It can also be used for the characterization and the direction of the real MTJ cells.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.38-47
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• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.345-345
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• 2010

1T-DRAM cell with solid phase (SPC) crystallized poly-Si thin film transistor was fabricated and electrical characteristics were evaluated. The fabricated device showed kink effect by negative back bias. Kink current is due to the floating body effect and it can be used to memory operation. Current difference between "1" state and "0" state was defined and the memory properties can be improved by using gate induced drain leakage (GIDL) current.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.03b
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• pp.40-40
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• 2010

CdSe nanocrystals (NCs) have been decorated on singlewalled carbon nanotubes (SWCNTs) by combining a method of chemically modified substrate along with gate-bias control. CdSe/ZnS core/shell quantum dots were negatively charged by adding mercaptoacetic acid (MAA). The silicon oxide substrate was decorated by octadecyltrichlorosilane (OTS) and converted to hydrophobic surface. The negatively charged CdSe NCs were adsorbed on the SWCNT surface by applying the negative gate bias. The selective adsorption of CdSe quantum dots on SWCNTs was confirmed by confocal laser scanning microscope. The measured photocurrent clearly demonstrates that CdSe NCs decorated SWCNT can be used for photodetector and solar cell that are operable over a wide range of wavelengths.

• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.187-189
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• 2015

A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×10⁵ and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm²/V·s at a drain voltage of −1 V, respectively.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1555-1557
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• 2002

We have investigated the precharge type sense amplifier, it is suitable fur voltage sensing in a NOR type single transistor ferroelectric field effect transistor (1T FeFET) memory read operation. The proposed precharge type sense amplifier senses the bit line voltage of 1T FeFET memory. Therefore, the reference celt is not necessary compared to current sensing in 1T FeFET memory, The high noise margin is wider than the low noise margin in the first inverter because requires tile output of precharge type sense amplifier high sensitivity to transition of input signal. The precharge type sense amplifier has very simple structure and can sense the bit line signal of the 1T FeFET memory cell at low voltage.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.849-852
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• 2007

We studied ZnO thin films deposited with DC magnetron sputtering for channel layer of TFTs. After analyzing of the basic physical and chemical properties of ZnO thin films, we fabricated a TFTunit test cell. The field effect mobility of $1.8\;cm^2/Vs$ and threshold voltage of -0.7 V were obtained.