• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.25-32
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• 2011

We have analyzed adjacent cell dependency of threshold voltage shift caused by the cell to cell interference, and we proposed a 3-adjacent-cell model to model the pattern dependency of the threshold voltage shift. The proposed algorithm is verified by using MATLAB simulation and measurement results. In the experimental results, we found that accuracy of the proposed simple 3-adjacient-cell model is comparable to the widely used conventional 8-adjacient-cell model. The Bit Error Rate (BER) of LSB and of MSB is improved by 28.9% and 19.8%, respectively, by applying the proposed algorithm based on 3-adjacent-cell model to 20nm-class 2-bit MLC NAND flash memories.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.87-94
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• 2001

A soft error rate for DRAM was predicted in connection with the leakage current in cell capacitor. The charge in cell capacitor was decreased during the DRAM operation, and soft error retes due to the leakage current were calculated in various operation mode of DRAM. It was found that the soft error rate of the /bit mode was dominant with small leakage current, but as increasing the leakage current memory mode shown the dominant effect on soft error rate. Using the 256M grade DRAM structure it was predicted that the soft error rate was influenced by the change of the cell capacitance, bit line capacitance, and the input voltage sensitivity of sense amplifier, and these results can be used to the design of the optimum cells in the next generation DRAM development.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.10a
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• pp.92-102
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• 1986

In this paper, Modular cell approach was applied to custom IC design or RS decoder. For the design of RS decoder by modular cells, 3 basic cells and one extra circuit are designed, these are, SYN cell for syndrome calculation, AL cell for error locator polynomial calculation, and REM cell for remaining error transform calculation. RS decoder design by these basic cells is very simple and regular, and naturally suitable for VLSI RS decoder design.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.179-181
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• 2005

There is asymmetric in horizontal and vertical side of PDP cell. Every vertical line has BM(Black Mask) to improve luminance contrast. When error diffusion is processed in PDP system, these problems make an error bigger. In 4 inch PDP system, every red, green, blue color of test pattern is presented and each luminance is measured. That is called horizontal(H), diagonal right(R), diagonal left(L) and vertical(V). In red channel, high luminance descending order is V-H-R-L. In green channel, V-H-L-R. In blue channel, V-M-R=L. After average luminance of each direction is calculated. new weighted error diffusion(Weighted ED) is proposed. In digital image signal processing, the error in weighted ED is differ from ED's. The image of weighted ED is more less error compare to conventional ED and close to original image. As the gray level linearity and big size panel is adopted, weighted ED could produce good image.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.10
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• pp.2687-2702
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• 1996

It is desirable that the implementation of next generation information infrastructure is the Integrated Network combining the satellite and the terrestrial network. The application of the ATM network being the dominant infrastrure of terrestrial network to the satellite network is being studied variously. Considering these concepts, this paper analyzes due to ATM transport via satellite, evaluates the degradation of QoS and proposes reliable method of ATM cell transport via satellite. Because ATM is investigated with the optical fiber which is almost error free characteristics, the practical application of ATM transport via satellite essentially need the channel coding(FEC:Forward Error Correction) to enhance BER performance. But using the FEC coding, satellite link has burst error characteristics which evoke severe performance degradation fo ATM QoS. Therefore in satellite link, we analyze burst error characteristics using experimental results of computer simulation. Then to compensate these characteristics, based on this analysis and HEC dual mode algorithm we propose various interleaver structures(Block interleaver, Intra interlever, and Inter-Intra interleaver) to improve cell transmission QoS. We execute performance evaluations of iterleaver structures by computer simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.2014-2026
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• 1997

In this paper, the performances of wireless asynchronous transfer mode (ATM) cell transmission in mobile work are analyzed. We adopt 16Star QAM as amodulation technique in wireless channel and considered Reed-Solomon, convolutional, and concatenated coding to improve the error rate performances, and also proposed the Partial Concatenated Coding (PCC) technique as UEP(unequal error protection) code for efficient transmission of ATM cell in the air interface. We consider Doppler's effect, Rician fading, and diversity technique of maximal-ratio combining (MRC) for mobile channel model. For performance measure, we analyze bit error rate, ATM cell loss probability, ATM cell error probability, and network performances of ATM cell transmission delay and throughput. The numerical results show that the adoption of PCC is a prospective way for the evolution of future wireless ATM network on mobile environment.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.6 no.3
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• pp.3-10
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• 1996

We present a method to recover consecutive cell losses using forward error correction(FEC) in ATM networks. Our method recovers up to 18 consecutive cell losses. Also, we present the performance estimation of the FEC technique using the interleaving in ATM networks. Performance estimation shows an outstanding reduction in cell loss rate.

• Journal of the Korean Society for Precision Engineering
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• v.15 no.8
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• pp.109-115
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• 1998

This paper describes the development of a 6-component load cell with plate beams which may be used to measure forces Fx, Fy, Fz and moments Mx, My, Mz simultaneously in industry. We have analyzed the bending strains on the surface of the beams under forces or moments by using Finite Element Method and designed the sensing elements of 6-component load cell. We have also determined the attachment location of strain gages of each load cell and fabricated 6-component load cell. To evaluate the rated strain and interference error of each load cell, we have carried out characteristic test of 6-component load cell.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.8-16
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• 2010

NAND multilevel cell (MLC) flash memory is widely issued because it can increase the capability of storage by storing two or more bits to a single cell. However if a number of levels in a cell increases, some physical features like cell to cell interference result cell voltage shift and it is known that a VT shift is unidirectional. To reduce errors by the effects, we can consider error correcting codes(ECC) or signal processing methods. We focus signal processing methods for the cell to cell interference voltage shift effects and propose the algorithms which reduce the effects of the voltage shift by estimating it and making level read voltages be adaptive. These new algorithms can be applied with ECC at the same time, therefore these algorithms are efficient for MLC error correcting ability. We show the bit error rate simulation results of the algorithms and compare the performance of the algorithms.

• Journal of information and communication convergence engineering
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• v.9 no.5
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• pp.615-618
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• 2011

Living cells generate the cell cycle or apoptosis, depending on the course will be repeated. If an error occurs during this period of life in order to maintain the cells in the peripheral cells find the error portion. These cellular functions were applied to the system to simulate the circuit. Circuit implementation of the present study was constructed the redundant structure in order to found the error quickly. Self-repairing of digital systems as an advanced form of fault-tolerance has been increasingly receiving attention according as digital systems have been more and more complex and speed-up especially for urgent systems or those working on extreme environments such as deep sea and outer space. Simulating the process of cell differentiation algorithm was confirmed by the FPGA on the counter circuit. If an error occurs on the circuit where the error was quickly locate and repair. In this paper, we propose a novel self-repair architecture for fast and robust fault-recovery that can easily apply to real, complex digital systems. These Self-Repairing Algorithms make it possible for the application digital systems to be alive even though in very noisy and extreme environments.