Cell to Cell Interference Cancellation Algorithms in Multi level cell Flash memeory |
Jeon, Myeong-Woon
(Department of Electrical and Computer Science Engineering, Seoul National University)
Kim, Kyung-Chul (Department of Electrical and Computer Science Engineering, Seoul National University) Shin, Beom-Ju (Hynix Inc.) Lee, Jung-Woo (Department of Electrical and Computer Science Engineering, Seoul National University) |
1 | Roberto Bez, Emilio Camerlenghi, Alberto Modelli, and Angelo Visconti, "Introduction to Flash Memory," IEEE Proc., vol. 91, NO.4, April 2003. |
2 | P. Pavan, R. Bez, P. Olivo, and E. Zanoni, "Flash memory cells-An overview," IEEE Proc., vol. 85, pp. 1248-1271, Aug. 1997. DOI ScienceOn |
3 | Calligaro C., Manstretta A., Modelli A. and Torelli G. "Technological and Design Constraints for Multilevel Flash Memories," ICECS '96, pp.1005-1008, 1996. |
4 | B. Ricco, G. Torelli, M. Lanzoni, A. Manstretta, H. E. Maes, D. Montanari, and A. Modelli, "Nonvolatile multilevel memories for digital applications," IEEE Proc., vol. 86, pp. 2399-2423, Dec. 1998. DOI ScienceOn |
5 | A. Modelli, R. Bez, and A. Visconti, "Multi-level Flash memory technology," Int. Conf. Solid State Devices and Materials(SSDM), pp. 516-517, Tokyo, Japan, 2001. |
6 | C. Calligaro, A. Manstretta, A. Modelli, and G. Torelli, "Technological and design constraints for multilevel Flash memories," in Proc. 3rd IEEE Int. Conf. Electronics, Circuits, and Systems, pp.1003-1008, 1996. |
7 | P. Cappelletti and A. Modelli, "Flash memory reliability," Flash Memories, P. Kluwer, pp. 399-441, 1999. |
8 | S. Aritome, R. Shirota, G. Hemnik, T. Endoh, and F. Masuoka, "Reliability issues of Flash memory cells," IEEE Proc., vol. 81, pp. 776-788, May 1993. DOI ScienceOn |
9 | Jae-Duk Lee, Sung-Hoi Hur and Jung-Dal Choi, "Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation," IEEE ElectronDevice Letters, vol. 23, no. 5, pp. 264-266, May 2002. |
10 | S. Gregori, A. Cabrini, O. Khouri, and G. Torelli, "On-chip error correcting techniques for new-generation Flash memories," IEEE Proc., vol. 91, no. 4, pp. 602-616, 2003. DOI ScienceOn |
11 | M. Grossi, M. Lanzoni, and B. Ricco, "Program schemes for multilevel Flash memories," IEEE Proc., vol. 91, no. 4, pp. 594-601, 2003. DOI ScienceOn |
12 | Y. Cassuto, M. Schwartz, V. Bohossian and J. Bruck, "Codes for multi-level flash memories: Correcting asymmetric limited-magnitude errors," Proc. IEEE Int. Symp. Information Theory (ISIT), p. 1176-1180, 2007. |