• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.40 no.6
• /
• pp.8-15
• /
• 2003

In this paper, the issue of the differential ring oscillator in designing low phase noise is linearity improvement of delay cell's load resistor. A novel differential delay cell that improves on the Maneatis load is proposed. The linearity improvement of load resistor results in lower phase noise in ring oscillator. For comparison of the phase noise characteristics, Ali Hajimiri's phase noise model is used. In order to have a low ISF(impulse sensitivity function), it is important to have a symmetry between rise time and fall time of oscillation waveform. The ISF value of ing oscillator based on the proposed delay cell is lower than that of the existing ring oscillators. Due to this result, the phase noise is improved by 2~3dBc/Hz for the same power dissipation and oscillation frequency.

• Molecules and Cells
• /
• v.41 no.5
• /
• pp.436-443
• /
• 2018

The actin cytoskeleton plays a key role in the entry of mitosis as well as in cytokinesis. In a previous study, we showed that actin disruption delays mitotic entry at G2/M by sustained activation of extracellular signal-related kinase 1/2 (ERK1/2) in primary cells but not in transformed cancer cell lines. Here, we examined the mechanism of cell cycle delay at G2/M by actin dysfunction in IMR-90 normal human fibroblasts. We observed that de-polymerization of actin with cytochalasin D (CD) constitutively activated ribosomal S6 kinase (RSK) and induced inhibitory phosphorylation of Cdc2 (Tyr 15) in IMR-90 cells. In the presence of an actin defect in IMR-90 cells, activating phosphorylation of Wee1 kinase (Ser 642) and inhibitory phosphorylation of Cdc25C (Ser 216) was also maintained. However, when kinase-dead RSK (DN-RSK) was overexpressed, we observed sustained activation of ERK1/2, but no delay in the G2/M transition, demonstrating that RSK functions downstream of ERK in cell cycle delay by actin dysfunction. In DN-RSK overexpressing IMR-90 cells treated with CD, phosphorylation of Cdc25C (Ser 216) was blocked and phosphorylation of Cdc2 (Tyr 15) was decreased, but the phosphorylation of Wee1 (Ser 642) was maintained, demonstrating that RSK directly controls phosphorylation of Cdc25C (Ser 216), but not the activity of Wee1. These results strongly suggest that actin dysfunction in primary cells activates ERK1/2 to inhibit Cdc2, delaying the cell cycle at G2/M by activating downstream RSK, which phosphorylates and blocks Cdc25C, and by directly activating Wee1.

• The KIPS Transactions:PartC
• /
• v.9C no.2
• /
• pp.277-282
• /
• 2002

In general, requirements for QoS are different according to the type of services in wire-line and wireless ATM networks, and real-time video service is more sensitive to cell transmission delay than to cell loss. Existing handoff schemes emphasizing prevention of cell loss had limitations in cell transmission delay to satisfy QoS. In this paper, a novel scheme to transmit ATM cells with low CLP(when CLP = 0) prior to others and discarding cells with high CLP(when CLF = 1) in ATM cell header among cells to be forwarded to new base station during handoffs in real-time VBR service is proposed. The proposed scheme is proven to be suitable for the satisfaction of QoS of real-time VBR service and appropriate for fast handoffs by giving high CLP value to less meaningful MPEG frames through simulations.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.4
• /
• pp.855-869
• /
• 1997

In this paper, we proposed two kids of dynamic priority control mechanisms controlling the cell service ratio in order to improve the QOS(Quality of Service). We also analyse theoretically the characteristics of cell loss probability and mean cell delay time by applying the proposed priority control mechanisms to ATM switch with output buffer. The proposed priority control mechanisms have the same principles of storing cells into buffer but the different principles of serving cells from buffer. The one is the control mechanism controlling the cell service ratio according to the relative cell occupancy ratio of buffer, the other is the control mechanism controlling the cell service ratio according to both the relative cell occupancy ratio of buffer and the average arrival rate. The two service classes of our concern are the delay sensitive class and the loss sensitive class. The analytical results show that the proposed control mechanisms are able to improve the QOS, the characteristics of cell loss probability and mean cell delay time, by selecting properly the relative cell occupancy ratio of buffer and the average arrival rate. conventional DLB algorithm does not support synchronous cells, but the proposed algorithm gives higher priority to synchronous cells. To reduce synchronous cell loss rate, the synchronous cell detector is used in the proposed algorithm. Synchronous cell detector detects synchronous cells, and passes them cells to the 2nd Leaky-Bucket. So it is similar to give higher priority to synchronous cells. In this paper, the proposed algorithm used audio/video traffic modeled by On/Off and Two-state MMPP, and simulated by SLAM II package. As simulation results, the proposed algorithm gets lower synchronous cell loss rate than the conventional DLB algorithms. The improved DLB algorithm for multimedia synchronization can be extended to any other cells which require higher priority.

• Journal of electromagnetic engineering and science
• /
• v.12 no.2
• /
• pp.166-170
• /
• 2012

This paper presents a tunable composite right/left-handed (CRLH) delay line for a delay line discriminator that linearizes modulated frequency sweep in a frequency modulated continuous wave (FMCW) radar transmitter. The tunable delay line consists of 8 cascaded unit cells with series varactor diodes and shunt inductors. The reverse bias voltage of the varactor diode controlled the group delay through its junction capacitance. The measured results demonstrate a group delay of 8.12 ns and an insertion loss of 4.5 dB at 250 MHz, while a control voltage can be used to adjust the group delay by approximately 15 ns. A group delay per unit cell of approximately 1 ns was obtained, which is very large when compared with previously published results. This group delay can be used effectively in FMCW radar transmitters.

• Journal of the Korea Society for Simulation
• /
• v.8 no.1
• /
• pp.51-61
• /
• 1999

A cell scheduling method of Queue for the ATM switch is proposed and simulated. In this paper, we present the cell scheduling method proper to the proposed queue and the improved queue with Queue Sharing(QS) structure for CBR, VBR, ABR traffic. The proposed QS structure minimizes the CLS(Cell Loss Ratio) of ABR traffic and decreases the CLR of bursty VBR traffic. Also we propose a cell scheduling method using VRR(Variable Round Robin) scheme proper to the high-speed(ATM) switch. The VRR scheme provides a fairness in terms of service chance for the queues in the ATM switch as well as QOS of their cell delay characteristic of CBR and VBR traffic, QOS of ABR CLR. The simulation results show the proposed method achieves excellent CLR and average cell delay performance for the various ATM traffic services in the Queue Sharing structure.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.5
• /
• pp.17-26
• /
• 1998

B-ISDN has many advantages to provide multimedia, image transfer, etc. Recently, ABR service has been proposed in order to satisfy user's various requirements in it. In this paper, we propose a new ABR flow control algorithm called CAPRO. This algorithm uses the buffer proportional to propagation delay and controls the traffic on a link-by-link basis in order to minimize the effect of propagation delay. In order to use buffer more efficienctly, we define the request cell and the control cell. Then, we analyze our algorithm using mathematical model, simulate it using SLAM system, and compare to the existing EPRCA. As a result, our algorithm has the benifit of the throughput, cell loss probability, and fairness.

• The Transactions of the Korea Information Processing Society
• /
• v.6 no.10
• /
• pp.2779-2789
• /
• 1999

In this paper, we propose a new neural Buffered Leaky Bucket algorithm for preventing the degradation of network performance caused by congestion and dealing with the traffic congestion in ATM networks. We networks. We justify the validity of the suggested method through performance comparison in aspects of cell loss rate and mean transfer delay under a variety of traffic conditions requiring the different QoS(Quality of Service). also, the cell scheduling algorithms such as DWRR and DWEDF used for multiplexing the incoming traffics are induced to get the delay time of the traffics fairly. The network congestion information from cell scheduler is used to control the predicted traffic loss rate of Neural Leaky Bucket, and token generation rate is changed by the predicted values. The prediction of traffic loss rate by neural networks can effectively reduce the cell loss rate and the cell transfer delay of next incoming cells and be applied to other traffic control systems. Computer simulation results performed for traffic prediction show that QoSs of the various kinds of traffics are increased.

• Journal of Korea Society of Industrial Information Systems
• /
• v.20 no.1
• /
• pp.1-7
• /
• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.132-135
• /
• 2000

We have been aware fer some time. that it is becoming harder to develop ASIC only, using the vendor wire model for the current top-down/bottom-up process. Because VDSM has a much bigger wired delay than cell delay, it is also difficult to reduce development time, as well as time-to-market, while developing several million gate ASIC's. The same is true for high frequency ASIC's with VDSM (which have larger wire delay versus cell delay). Therefore, a solution called “RTS-GDS”, using physical constraints fur SOC with timing met, is being actively discussed. This paper suggests a methodology for SOC development by utilizing a top down flow via CWLM along with discussing potential problems. This paper also provides a design flow, including physical synthesis, DFT, floor plan and CWLM, all of which are relevant to proper SOC development.