• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.522-529
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• 2002

MMIC circuits in whole receiver system was fabricated based on GaAs pHEMT technology. And a V-band downconverter module was fabricated by integrating these circuits. The downconverter module consists of a LO drive power amplifier which generates 24dBm output power, a low noise amplifier(LNA) which shows 20 dB small signal gain, an active parallel feedback oscillator which generates 1.6 dBm output power, and a cascode mixer which shows over 6dB conversion gain. The good conversion gain performance of our mixer made no need to attach any IF amplifier which grows conversion gain. Measured results of the complete downconverter show a conversion gain of over 20 dB between 57.5 GHz and 61.7GHz without IF amplifier.

• ETRI Journal
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• v.42 no.5
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• pp.773-780
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• 2020

A 40 nm complementary metal oxide semiconductor carrier-aggregated drive amplifier with high linearity is presented for sub-GHz Internet of Things applications. The proposed drive amplifier consists of two high linear amplifiers, which are composed of five differential cascode cells. Carrier aggregation can be achieved by switching on both the driver amplifiers simultaneously and combining the two independent signals in the current mode. The common gate bias of the cascode cells is selected to maximize the output 1 dB compression point (P1dB) to support high-linear wideband applications, and is used for the local supply voltage of digital circuitry for gain control. The proposed circuit achieved an output P1dB of 10.7 dBm with over 22.8 dBm of output 3rd-order intercept point up to 0.9 GHz and demonstrated a 55 dBc adjacent channel leakage ratio (ACLR) for the 802.11af with -5 dBm channel power. To the best of our knowledge, this is the first demonstration of the wideband carrier-aggregated drive amplifier that achieves the highest ACLR performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.11
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• pp.834-841
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• 2018

A power amplifier for subgigahertz short-range wireless communication using $0.18-{\mu}m$ CMOS technology is presented. It is designed as a differential structure to form easily a virtual ground node, to increase output power, and to design a cascode structure to prevent breakdown. The transistor gate width was determined to maximize the output power and power-added efficiency(PAE), and the balun was optimized through electromagnetic simulation to minimize the loss caused by the matching network. This power amplifier had a gain of more than 49.5 dB, a saturation power of 26.7 dBm, a peak PAE of 20.7 % in the frequency range of 860 to 960 MHz, and a chip size of $2.14mm^2$.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1601-1602
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• 2006

A cascode low noise amplifier(LNA) for a 2.45GHz RFID reader is designed using 0.25um CMOS technology. There are four LNA design techniques applied to the cascode topology. In this paper, power-constrained simultaneous noise and input matching(PCSNIM) technique is used for low power consumption and achieving the noise matching and input matching simultaneously. Simulation results demonstrate a noise figure of 2.75dB, a power gain of 10.17dB, and a dissipation power of 8.65mW with 1V supply.

• Transactions on Electrical and Electronic Materials
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• v.15 no.3
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• pp.149-154
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• 2014

A new CMOS analog design methodology using an independently optimized self-cascode (SC) is proposed. This idea is based on the concept of the dual-workfunction-gate MOSFETs, which are equivalent to SC structures. The channel length of the source-side MOSFET is optimized, to give higher transconductance ($g_m$) and output resistance ($r_{out}$). The highest $g_m$ and $r_{out}$ of the SC structures are obtained by independently optimizing the channel length ratio of the SC MOSFETs, which is a critical design parameter. An operational amplifier (OPAMP) with the proposed design methodology using a standard digital $0.18-{\mu}m$ CMOS technology was designed and fabricated, to provide better performance. Independently $g_m$ and $r_{out}$ optimized SC MOSFETs were used in the differential input and output stages, respectively. The measured DC gain of the fabricated OPAMP with the proposed design methodology was approximately 18 dB higher, than that of the conventional OPAMP.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.947-950
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• 2003

본 논문에서는 고속 적외선 무선 데이터통신(IrDA) 에 사용되는 트랜스임피던스 증폭기(Transimpedance Amplifier)를 설계하였다. 트랜스임피던스 증폭기는 잡음을 최소화하기 위해 PMOS 차동 구조로 설계하였으며 입력과 출력의 피드백을 통해 주위의 빛에 의해 발생되는 photocurrent 에 의한 DC 옵셋을 제거하였다 또한 공통 게이트(CG)와 Regulated Cascode Circuit (RGC)을 추가하여 대역폭(Bandwidth)을 향상시켰다. 설계한 회로는 0.25 um CMOS 공정을 이용하였으며 트랜스임피던스 이득은 200 MHz의 대역폭에서 10 KΩ (80 dBΩ )이다. 전체 전력 소비는 18 mW이다.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1163-1166
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• 1999

In this paper, A CMOS power amplifier for PCS is designed with 0.65-$\mu\textrm{m}$ CMOS technology. Differential cascode structure is used which has good reverse isolation and wide voltage swing. This amplifier circuits consist of three stages which are power amplification stage, driver stage and power control stage. We obtain output power of 30 ㏈m, IMD3 of -31㏈c and efficiency of 30 % at input power of 4 ㏈m.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.341-342
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• 2007

The IRFPA (InfraRed Focal Plane Array) ROIC (ReadOut Integrated Circuit) was designed in folded-cascode Op-Amp using $0.35{\mu}m$ CMOS technology. As the folded-cascode has high open-loop voltage gain and fast settling time, that used in many analog circuit designs. In this paper, folded-cascode Op-Amp for ROIC of the $32{\times}32$ IRFPA has been designed. HSPICE simulation results are unit gain bandwidth of 13.0MHz, 90.6 dB open loop gain, 8 V/${\mu}m$ slew rate, 600 ns settling time and $66^{\circ}$ phase margin.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.505-506
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• 2006

In this paper, the linearization technique for CMOS low-noise amplifier (LNA) using the derivative superposition method through the multiple gated transistors configuration is presented. LNA based on 0.13um RF CMOS process has been implemented with a modified cascode configuration using multiple gated common source transistors to fulfill a high linearity. Compared with a conventional cascode type LNA, the third order input intercept point (IIP3) per DC power consumption (IIP3/DC) is improved by 3.85 dB. The LNA achieved 2.5-dBm IIP3 with 13.4-dB gain, 3.6 dB NF at 2.4 GHz consuming 8.56 mA from a 1.5-V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6A
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• pp.697-704
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• 2004

This paper describes the design and fabrication of an MMIC variable gain LNA for 5GHz wireless LAN applications, using 0.5${\mu}{\textrm}{m}$ gate length GaAs MESFET transistors. The advantages of high gain and low noise performance of E-MESFETS and excellent linear performance of D-MESFETS are combined as a cascode topology in this design. Behavioral model equations are derived from the MESFET nonlinear current voltage characteristics by using Turlington's asymptote method in a cascode configuration. Using the behavioral model equations, a 4${\times}$50${\mu}{\textrm}{m}$ E-MESFET as a common source amplifier and a 2${\times}$50${\mu}{\textrm}{m}$ D-MESFET as a common gate amplifier are determined for the cascode amplifier. The fabricated variable gain LNA shows a noise figure of 2.4dB, variable gain range of more than 17dB, IIP3 of -4.8dBm at 4.9GHz, and power consumption of 12.8mW.