• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.4
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• pp.367-370
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• 2004

We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing $0.35\mu{m}$ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/ silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed $200\AA$and $300\AA$-thick capping silicon, and varied the EDR process condition at temperature of $900-1000^\circ{C}$, and time of 0-30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be $975^\circ{C}$-30 sec with $300\AA$-thick capping silicon for proposed $0.35\mu{m}$-SiGe HBT devices.

• Journal of the Korean Vacuum Society
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• v.9 no.4
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• pp.335-340
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• 2000

We investigated the role of the capping layers in the formation of the cobalt silicide in Co/Si systems with TiN and Ti capping layers and without capping layers. The Co/Si interfacial reactions and the phase transformations by the rapid thermal annealing (RTA) processes were observed by sheet resistance measurements, XRD, SIMS and TEM analyses for the clean silicon substrate as well as for the chemically oxidized silicon substrate by $H_2SO_4$. We observed the retardation of the cobalt disilicide formation in the Co/Si system with Ti capping layers. In the case of Co/$SiO_2$/Si system, cobalt silicide was formed by the Co/Si reaction due to with the dissociation of the oxide layer by the Ti capping layers.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.05a
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• pp.349-350
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• 2012

Porous silicon (PS) was prepared by electrochemical anodization. Ultra-thin zinc oxide (ZnO) capping layers were deposited on the PS by plasma-assisted molecular beam epitaxy (PA-MBE). The effects of the ZnO capping layers on the properties of the as-prepared PS were investigated using scanning electron microscopy (SEM) and photoluminescence (PL). The as-prepared PS has circular pores over the entire surface. Its structure is similar to a sponge where the quantum confinement effect (QCE) plays a fundamental role. It was found that the dominant red emission of the porous silicon was tuned to white light emission by simple deposition of the ultra-thin ZnO capping layers. Specifically, the intensity of white light emission was observed to be enhanced by increasing the growth time from 1 to 3 min.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.57-62
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• 1999

Polycrystaline thin film transistors are fabricated on the transparent glass substrate by a lamp-scan annealing. The line-shaped lamp scanning method, which is profitable for large area process, effectively radiated silicon film on glass substrate. Amorphous silion film absorbs the light which is emitted from halogen-lamp and it transformed into crystalline silicon by metal-induced lateral crystallization. In order to enhance the annealing effect, capping layer was deposited on the whole substrate. When the scan speed was 1-2mm/sec, lateral crystallization of amorphous silicon under capping layer was 18~27${\mu}m/scan$. The thin film transistor fabricated by this method shows high electron mobility over 130$cm^2/V{\cdot}sec$

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.245-248
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• 2002

In this paper, the influence of Si surface damage on the NiSi formation has been characterized. The silicon surface is damaged using ion beam type spotter. Then, the effect of H2 anneal and TiN capping layer on the damaged has also been analyzed. The sheet resistance of NiSi formed on damaged Si increased rapidly as the damaging time increases while thermal stability of damaged NiSi was stabler than the undamaged one. In the case when H\ulcorner anneal and TiN capping layer were applied together, the characteristics of NiSi shows a little improvement of the sheet resistance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.167-170
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• 2002

The influence of Si surface damage on Ni-silicide with TiN Capping layer and the effect of $H_2$ anneal are characterized. Si surface is intentionally damaged using Ar Sputtering. The sheet resistance of NiSi formed on damaged silicon increased rapidly as Ar sputtering time increased. However, the thermal stability of Ni-Si on the damage silicon was more stable than that on at undamaged Si, which means that damaged region retards the formation of NiSi. It was shown that $H_2$ anneal and TiN capping is highly effective in reducing NiSi sheet resistance.

• Journal of the Semiconductor & Display Technology
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• v.10 no.1
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• pp.57-61
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• 2011

To develop high efficiency crystalline solar cells, the rear surface passivation is very important. In this paper, $Al_2O_3$ films deposited by thermal ALD(atomic layer deposition) method were studied for rear surface passivation of crystalline solar cells and their passivation properties were evaluated. After the deposition of $Al_2O_3$ films on p-type Si wafers, the lifetime was increased very much due to the reduction of interface state density and the field effects of the negative fixed charge in the films. Also, optimum annealing condition and effects of SiNx capping layer were investigated. The best lifetime was obtained when the films were annealed at $400^{\circ}C$ for 15min. And the lifetime degradation of the $Al_2O_3$ films with SiNx capping layers was improved compared to those without the capping layers.

• Journal of Integrative Natural Science
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• v.3 no.3
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• pp.133-137
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• 2010

New synthetic route and characterization of alkyl-capped nanocrystalline silicon (R-n-Si) were achieved from the reaction of silicon tetrachloride with sodium/benzophenone ketal reducing agent followed by n-butyllithium. Surface of silicon nanoparticles was derivatized with butyl group. Effect of oxidation of silicon nanoparticle with benzophenone was investigated for their stabilization. Optical characteristics of silicon nanoparticles were characterized by fourier transform infrared spectroscopy (FT-IR), ultraviolet-visible spectroscopy (UV-vis), and photoluminescence (PL) spectroscopy. Butyl-capped silicon nanoparticles exhibited an emission band at 410 nm with excitation wavelength of 360 nm. Average size of n-butyl-capped silicon nanoparticles was obtained by particle size analyzer (PSA) and transmission electron microscopy (TEM). Average size of n-butyl-capped Si nanoparticles was about 6.5 nm.

• Journal of Information Display
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• v.10 no.3
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• pp.117-120
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• 2009

A new crystallization method for amorphous silicon, called selective area heating (SAH), was proposed. The purpose of SAH is to improve the reliability of amorphous silicon films with extremely low thermal budgets to the glass substrate. The crystallization time shortened from that of the conventional solid-phase crystallization method. An isolated thin heater for SAH was fabricated on a quartz substrate with a Pt layer. To investigate the crystalline properties, Raman scattering spectra were used. The crystalline transverse optic phonon peak was at about 519 $cm^{-1}$, which shows that the films were crystallized. The effect of the crystallization time on the varying thickness of the $SiO_2$ films was investigated. The crystallization area in the 400nm-thick $SiO_2$ film was larger than those of the $SiO_2$ films with other thicknesses after SAH at 16 W for 2 min. The results show that a $SiO_2$ capping layer acts as storage layer for thermal energy. SAH is thus suggested as a new crystallization method for large-area electronic device applications.

• Electrical & Electronic Materials
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• v.7 no.4
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• pp.331-340
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• 1994

Polysilicon on insulator has been recrystallized by zone melting recrystallization method with graphite strip heaters. Experiments are performed with non-seed SOI structures. When the capping layer thickness of Si$\_$3/N$\_$4//SiO$\_$2/ is 2.0.mu.m, grain boundaries are about 120.mu.m spacing and protrusions reduced. After the seed SOI films are annealed at 1100.deg. C in NH$\_$3/ ambient for 3 hours, the recrystallized silicon surface has convex shape. After ZMR process, the tensile stress is 2.49*10$\^$9/dyn/cm$\^$2/ and 3.74*10$\^$9/dyn/cm$\^$2/ in the seed edge and seed center regions. The phenomenon of convex shape and tensile stress difference are completely eliminated by using the PSG/SiO$\_$2/ capping layer. The characterization of SOI films are showed that the SOI films are improved in wetting properties. N channel SOI MOSFET has been fabricated to investigate the electrical characteristics of the recrystallized SOI films. In the 0.7.mu.m thickness SOI MOSFET, kink effects due to the floating substrate occur and the electron mobility was calculated from the measured g$\_$m/ characteristics, which is about 589cm$\^$2//V.s. The recrystallized SOI films are shown to be a good single crystal silicon.