• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.699-705
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• 2008

Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.

• Proceedings of the KIEE Conference
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• 1997.07c
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• pp.1009-1011
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• 1997

This paper presents an optimization method which determines locations and size of capacitors simultaneously while minimizing power losses and improving voltage profile in radial distribution systems. Especially, the cost function associated with capacitor placement is considered as step function due to banks of standard discrete capacities. Genetic algorithms(GA) are used to obtain efficiently the solution of the cost function associated with capacitors which is non-continuous and non-differentiable function. The strings in GA consist of the node number index and size of capacitors to be installed. The length mutation operator, which is able to change the length of strings in each generation, is used. The proposed method which determines locations and size of capacitors simultaneously can reduce power losses and improve' voltage profile with capacitors of minimum size. Its efficiency is proved through the application in radial distribution systems.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.370-371
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• 2011

This paper presents a control algorithm that minimizes the DC-link capacitance by decreasing the capacitor current. The capacitor current can be nullified by a feedback compensation term which is calculated from the power balance in the AC/DC converter. As a result, voltage variation in the DC-link is reduced further, which makes a large reduction in the size of DC-link capacitors which are expensive and have limitations in life time. Simulations are performed with two 80uF DC-link capacitors, which can be replaced by film capacitors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.147-148
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• 2006

Ge nanocrystals(NCs)-embedded MOS capacitors are charactenzed in this work using capacitance-voltage measurement. High-k dielectrics $HfO_2$ are employed for the gate material m the MOS capacitors, and the C-V curves obtained from $O_2-$ and $NH_3$-annealed $HfO_2$ films are analyzed.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.2
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• pp.61-67
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• 2002

The number of passive components used in hand held devices and computers continue to increase so that the passive to active ratio continues to grow. Embedded passives are the best technology for very high component density with increased electrical performance. improved reliability, reduced size, weight and lower cost. Specially embedded capacitors are strongly under development. This paper discusses dielectric materials used in embedded capacitors and remained challenges.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1235-1243
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• 2015

This paper presents a modified Space Vector Pulse Width Modulation Technique (SVPWM), which solves the well-known problem of voltage imbalance in the capacitors of a single-phase multilevel inverter. The proposed solution is based on the measurement of DC voltage levels at each capacitor of the inverter DC bus. The measurements are then used to adjust the size of the active vectors within the SVPWM algorithm to keep the voltage waveform sinusoidal regardless of any voltage imbalance on the DC link capacitors. When a voltage deviation exceeds a predetermined hysteresis band, the correspondent voltage vector is restricted to restore the voltage level to an acceptable threshold. Hence, the need for external voltage regulators for the voltage capacitors is eliminated. The functionality of the proposed algorithm is successfully demonstrated through simulations and experiments on a grid tied application.

• Journal of Power Electronics
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• v.8 no.3
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• pp.275-279
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• 2008

An LLC series resonant converter has many unique characteristics and improvements over PWM topologies. However, many output capacitors are needed in parallel to satisfy output voltage ripple and the rated ripple current of the capacitors. This paper deals with a novel two phase interleaved LLC resonant converter using a phase of the resonant capacitor. The proposed converter can satisfy output voltage ripple and a rated ripple current of capacitors with few output capacitors, relatively. The operation and features are considered in detail and a prototype with a 12V-100A output is investigated.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.2
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• pp.209-215
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• 2018

This paper present a 7-level PWM inverter adopting voltage balancing control to series-connected input capacitors. The prior proposed 7-level PWM inverter consists of dc input source, three series-connected capacitors, two bidirectional switch modules, and an H-bridge. This circuit topology is useful to increase the number of output voltage levels, however it fails to generate 7-level in output voltage without consideration for voltage balancing among series-connected capacitors. Capacitor voltage imbalance is caused on the different period between charging and discharging of capacitor. To solve this problem, we uses the amplitude modulation of carrier wave, which is used to produce the center output voltage level. To verify the validity of the proposed control method, we carried out computer-aided simulation and experiments using a prototype.

• Journal of the Korean Society for Heat Treatment
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• v.15 no.3
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• pp.113-117
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• 2002

Fatigue characteristics of ferroelectric $Pb(Zr,Ti)O_3$ (PZT) based capacitors through donor doping is reported in this paper. La substitution up to 10% were carried out to study systematically the fatigue behaviors of epitaxial ferroelectric capacitors grown on Si using $(Ti_{0.9}Al_{0.1})N/Pt$ conducting barrier composite. Ferroelectric capacitors substituted with 10% La show sufficient low voltage switched polarization and fatigue free performance. Systematic decrease in the tetragonality of the ferroelectric phase (i.e., c/a ratio) results in the corresponding reduction in coercive voltage, sufficient remnant polarization at 1.5-3V, and good fatigue property.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.526-528
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• 2008

LLC series resonant converter has many unique characteristics and improvement over PWM topologies. However, many output capacitors should be needed in parallel to satisfy an output voltage ripple and a rated ripple current of the capacitors. This paper is deal with a novel two phase interleaved LLC resonant converter using a phase of the resonant capacitor. The proposed converter can satisfy output voltage ripple and a rated ripple current of capacitors with few output capacitors, relatively. The operation and features is considered in detail and a prototype with a 12V-100A output is investigated.