• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1720-1725
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• 2015

The performance of the AlGaN/GaN MSM-2DEG varactor with different dielectric films deposited by the E-beam deposition is investigated in detail. The capacitance swing and the capacitance ratio of the varactor without dielectric film as well as with, SiO₂, Gd₂O₃, and Si₃N₄ films, respectively, are determined by electrodes of varying areas. The maximum capacitance, the minimum capacitance and the capacitance ratios are proportional to the increasing of the electrode areas. The capacitance ratio determined by the maximum and the minimum capacitance is found to be 18.35 (with Si₃N₄ dielectric film) and 149.51 (without dielectric film), respectively. The transition voltages of the fabricated varactors are almost the same for a bias voltage of about ±5 V and leakage current can be lower three orders of magnitude while the varactors with dielectric films. The tunability of the capacitance ratio makes the AlGaN/GaN MSM-2DEG varactor with a dielectric film highly useful in multirange applications of a surge free preamplier.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.989-998
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• 2012

A ratio type of capacitance measurement circuit is proposed to measure an extremely small value of the fF capacitance on this paper. This measurement circuit is formed with a switched-capacitor integrator, a comparator, and logic circuit blocks to control the switches. It converts the measured ratio value between the known value of on-chip capacitor and the unknown value of capacitor to the digital signal. The fF capacitance with minimized error can be obtained by calculating this ratio. This proposed circuit is designed with standard CMOS $0.18{\mu}m$ process, and various HSpice simulations prove that this capacitance measurement circuit is able to measure the capacitance under 5fF with less than ${\pm}0.3%$ error rate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.102-104
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• 1996

The fabrication and analytical expression for the temperature dependent capacitance characteristics of inverted staggered hydrogenerated amorphous silicon thin film transistors(a-si :H TFT) from 303k to 363k were presented. The results show that the experimental capacitance-voltage characteristics at several temperatures are easily measured. Capacitance increased exponentially by gate voltage increase and decreased by temperature increase. C/C(max) ratio decreased at higher temperature, C/C(min) ratio increased at higher temperature.

• Proceedings of the Safety Management and Science Conference
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• 2003.11a
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• pp.343-350
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• 2003

The best Ppy weight ratio was 7 wt% and the optimal electrode composition ratio was 78 : 17 : 5 wt.% of (MSP-20 : BP-20 =1 : 1), (Super P : Ppy =10 : 7) and P(VdF-co-HFP). Implantation of Ppy as the conducting agents have led to superior electrochemical characteristics because of the low of internal resistance and faradaic capacitance. The result of unit cell with Ppy 7 wt% were as follows: 28.02 Fig of specific capacitance, 1.34 Ω of DC-ESR and 0.36 Ω of AC-ESR. Unit cell showed a good stability up to 200 charge-discharge cycles, retaining 82% of their original capacity at 200 cycles. From the analysis of impedance, the electrodes with Ppy 7 wt% showed low ESR, low charge transfer resistance and quick reaction rate. It was inferred that quick charge-discharge was possible. As compared with the specific capacitance (rectangular shape) of CV, it was also concluded that the specific capacitance originated from thecompound phenomena of the faradaic capacitance by oxidation and reduction of Ppy and the non-faradaic capacitance by adsorption-desorption of activated carbon.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.45-49
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• 2022

Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• Journal of the Korean Applied Science and Technology
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• v.24 no.4
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• pp.377-382
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• 2007

We designed capacitance sensor in order to examine characteristics of W/O type emulsified fuel, so it concluded the following conclusions. The capacitance value of emulsified fuel, using with capacitance sensor, increases as water content increases due to the coalescence. When surfactant increases, the capacitance value decreases, the condition of W/O type emulsified fuel was maintained stably. There was revealed the capacitance value difference of W/O type emulsified fuel in in according to water content. We checked the phase separation of emulsified fuel with the capacitance value difference. The surfactant(HLB=5.4) had better stable condition than surfactant(HLB=4.3). Also, we confirmed that two mixture surfactants were better than one surfactant.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.3
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• pp.134-141
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• 2006

A potential transformer(PT) has ratio error and phase angle error. Precise measurement of the errors of PT can be achieved using high voltage capacitance bridge, high voltage capacitor and low voltage capacitor. The uncertainty for this method is evaluated and found to be $20{\times}10^{-6}$ in both ratio error and phase angle error. The values measured for PT using the method are well consistent with the those measured for same PT in NMIA(National Measurement Institute of Australia) within the corresponding uncertainty.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1561-1564
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• 2004

A CMOS-based Electronically Tunable Capacitance Multipliers, which can be magnified the value of a grounded unit capacitance, is presented in this article. The multiplication factor is varied by the ratio of the bias currents. The proposed circuit is simple, small in size and suitable for implementing in standard CMOS process. PSPICE simulation results demonstrating the characteristics of the proposed circuit are included.

• Journal of the Korean Applied Science and Technology
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• v.28 no.1
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• pp.95-101
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• 2011

We estimated on the stability of W/O type emulsified fuel using by capacitance sensor, so it concluded the following conclusions. For the first 24 hours, prepared emulsified fuel reveals phase separation ratio of 5%, maintains stable status which verifies the stability of emulsified fuel. Adding more water increases the phase separation ratio rapidly, and adding more surfactant displays stable emulsification. Adding water causes larger size of water droplet diameter, and adding surfactant mixture causes smaller size of water droplet diameter. In conclusion, the size of W/O type emulsified fuel water droplet diameter is directly related to the volume of surfactant, and density of water droplet diameter changes thedistribution according to water contents.