• Transactions on Electrical and Electronic Materials
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• 제11권3호
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• pp.120-125
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• 2010

For the fabrication of PMOS and integrated semiconductor devices, B, $BF_2$ and dual elements with B and $BF_2$ can be implanted in silicon. 15 keV B ions were implanted in silicon at $7^{\circ}$ wafer tilt and a dose of $3.0{\times}10^{16}\;cm^{-2}$. 67 keV $BF_2$ ions were implanted in silicon at $7^{\circ}$ wafer tilt and a dose of $3.0{\times}10^{15}\;cm^{-2}$. For dual implantations, 67 keV $BF_2$ and 15keV B were carried out with two implantations with dose of $1.5{\times}10^{15}\;cm^{-2}$ instead of $3.0{\times}10^{15}\;cm^{-2}$, respectively. For the electrical activation, the implanted samples were annealed with rapid thermal annealing at $1,050^{\circ}C$ for 30 seconds. The implanted profiles were characterized by using secondary ion mass spectrometry in order to measure profiles. The implanted and annealed results show that concentration profiles for the ${BF_2}^+$ implant are shallower than those for a single $B^+$ and dual ($B^+$ and ${BF_2}^+$) implants in silicon. This effect was caused by the presence of fluorine which traps interstitial silicon and ${BF_2}^+$ implants have lower diffusion effect than a single and dual implantation cases. For the fabricated diodes, current-voltage (I-V) and capacitance-voltage (C-V) were also measured with HP curve tracer and C-V plotter. Electrical measurements showed that the dual implant had the best result in comparison with the other two cases for the turn on voltage characteristics.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1284-1287
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• 2005

Peripheral pentacene region gives a significant influence on C-V characteristics of metal-oxide-pentacene capacitor structure. When the gate voltage goes toward negative, the effect of peripheral pentacene region becomes larger. Remaining gate DC bias constant and changing small signal frequency, the capacitance of peripheral pentacene changes along with frequency so that the total capacitance value also changes. The influence of peripheral pentacene region should be removed to measure accurate C-V characteristics, because it is hard to take into account the effect of the region quantitatively. After removing the influence of peripheral pentacene region, acceptor concentration, flat band voltage and depletion width of pentacene thin film are extracted from an accurate C-V curve as $1.58{\times}10^{17}cm^{-3}$, -1.54 V and 39.4 nm, respectively.

• 전자공학회논문지C
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• 제36C권7호
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• pp.10-16
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• 1999

본 논문은 FCSR(Freedback Control Swing voltage Reduction) 방식을 이용하여 bus 구동전압을 수백 mV이내로 줄일 수 있는 구동기에 대한 내용을 다루고 있다. 이는 MDL 구조와 같이 대용량, 대단위 bus에서의 전력소모를 줄이기 위한 연구로 FCSR은 dual-line bus와 bus precharging을 기본구조로 채택하고 있다. Bus 환경이 변화함에 따라 일정한 구동전압을 유지하기 위하여 구동기의 크기를 자동적으로 조절할 수 있도록 구동기와 bus를 모델링 하였고 또한 odd mode로 동작하는 이웃하는 선간의 커플링 영향을 평행 전류원으로 모델링하여 선간간섭(crosstalk) 영향을 분석하였다. 현대 0.8um 공정으로 제작된 chip은 bus를 600mV로 구동하도록 설계되었으며 테스트결과 3.3V에서 70Mhz로 동작 가능하다. Hspice 시뮬레이션으로 FCSR은 3.3V에서 250Mhz의 동작이 가능하다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• 센서학회지
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• 제23권3호
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• pp.185-191
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• 2014

The width of depletion region in a varactor diode can be modulated by varying a reverse bias voltage. Thus, the preferred characteristics of depletion capacitance can obtained by the change in the width of depletion region so that it can select only the desirable frequencies. In this paper, the TV tuner varactor diode fabricated by hyper-abrupt profile control technique is presented. This diode can be operated within 3.3 V of driving voltage with capability of UHF band tuning. To form the hyperabrupt profile, firstly, p+ high concentration shallow junction with $0.2{\mu}m$ of junction depth and $1E+20ions/cm^3$ of surface concentration was formed using $BF_2$ implantation source. Simulation results optimized important factors such as epitaxial thickness and dose quality, diffusion time of n+ layer. To form steep hyper-abrupt profile, Formed n+ profile implanted the $PH_3$ source at Si(100) n-type epitaxial layer that has resistivity of $1.4{\Omega}cm$ and thickness of $2.4{\mu}m$ using p+ high concentration Shallow junction. Aluminum containing to 1% of Si was used as a electrode metal. Area of electrode was $30,200{\mu}m^2$. The C-V and Q-V electric characteristics were investigated by using impedance Analyzer (HP4291B). By controlling of concentration profile by n+ dosage at p+ high concentration shallow junction, the device with maximum $L_F$ at -1.5 V and 21.5~3.47 pF at 0.3~3.3 V was fabricated. We got the appropriate device in driving voltage 3.3 V having hyper-abrupt junction that profile order (m factor) is about -3/2. The deviation of capacitance by hyper-abrupt junction with C0.3 V of initial capacitance is due to the deviation of thermal process, ion implantation and diffusion. The deviation of initial capacitance at 0.3 V can be reduced by control of thermal process tolerance using RTP on wafer.

• 한국진공학회지
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• 제10권4호
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• pp.440-448
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• 2001

논문에서는 원통형 및 평판형 반응기에 20 kV의 사각파형 펄스전원을 인가하여 대기압 절연막 방전 플라즈마 반응기의 동작특성을 관찰하였다. 전류-전압파형과 하전량-전압곡선을 관찰한 결과 반응기의 정전용량 크기에 따라서 최적의 운전효율을 갖는 최적운전주파수 $f_0$가 $f_0\proptoexp(-C)$의 관계를 갖고 있음을 알았다. 이 관계를 이용하여 반응기에서 소실되는 소모전력을 구하였다. 반응기의 소모전력은 반응기의 구조와 전극의 유전물질의 종류 등의 함수인 반응기 정전용량 값에 따라서 변화하였으며 반응기의 특정한 정전용량 값에서 최대값을 가졌다. 이 정전용량 값을 이용하여 최적효율을 갖는 DBD 반응기를 설계할 수 있을 것으로 사료된다.

• 한국전기전자재료학회논문지
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• 제23권4호
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• pp.311-316
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• 2010

$Zr_{0.7}Sn_{0.3}TiO_4$ (ZST) thin films were fabricated by metal-organic decomposition, and their dielectric properties were investigated in order to evaluate their potential use in passive capacitors for rf and analog/mixed signal integrated circuits. The ZST thin film annealed at the temperature of $800^{\circ}C$ showed a dielectric constant of 27.3 and a dielectric loss of 0.011. The capacitor using the ZST film had quadratic and linear voltage coefficient of capacitance (VCC) of -65 ppm/$V^2$ and -35 ppm/V at 100 kHz, respectively. It also exhibited a good temperature coefficient of capacitance (TCC) value of -32 ppm/$^{\circ}C$ at 100 kHz.

• 한국전기전자재료학회논문지
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• 제21권8호
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• pp.711-714
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• 2008

Metal-oxide-semiconductor (MOS) capacitors were fabricated to investigate the plasma damage caused by reactive ion etching (RIE) on (100) oriented silicon-on-insulator (SOI) substrates. The thickness of the top-gate oxide, SOI, and buried oxide layers were 10 nm, 50 nm, and 100 nm, respectively. The MOS/SOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching. The measured C-V curves were compared to the numerical results from corresponding 2-dimensional (2-D) structures by using a Silvaco Atlas simulator.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.785-787
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• 1988

The capacitance-voltage (C-V) chracteristics of thin nitrided thermal oxides prepared by rapid termal nitridation(RTN) have been studied. The threshold voltages were calculated using C-V measurement and found to vary as the concentration of acceptor and the thickness of oxynitride. When the Si02 films were annealed in NH3 a decrease in the positive oxide charge due to Si-N bond was observed. In the case applied frequency is high and low, the high frequency depletion capacitance was higher than that of low frequency, which is indicative of high frequency surface conduction by mobile surface charge.

• Journal of Electrical Engineering and Technology
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• 제9권1호
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• pp.280-285
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• 2014

In order to evaluate the insulation deterioration in the stator windings of five gas turbine generators(137 MVA, 13.8 kV) which has been operated for more than 13 years, diagnostic test and AC dielectric breakdown test were performed at phases A, B and C. These tests included measurements of AC current, dissipation factor, partial discharge (PD) magnitude and capacitance. ${\Delta}I$ and ${\Delta}tan{\delta}$ in all three phases (A, B and C) of No. 1 generator stator windings showed that they were in good condition but PD magnitude indicated marginally serviceable and bad level to the insulation condition. Overall analysis of the results suggested that the generator stator windings were indicated serious insulation deterioration and patterns of the PD in all three phases were analyzed to be internal, slot and spark discharges. After the diagnostic test, an AC overvoltage test was performed by gradually increasing the voltage applied to the generator stator windings until electrical insulation failure occurred, in order to determine the breakdown voltage. The breakdown voltage at phases A, B and C of No. 1 generator stator windings failed at 28.0 kV, 17.9 kV, and 21.3 kV, respectively. The breakdown voltage was lower than that expected for good-quality windings (28.6 kV) in a 13.8kV class generator. In the AC dielectric breakdown and diagnostic tests, there was a strong correlation between the breakdown voltage and the voltage at which charging current increases abruptly ($P_{i1}$, $P_{i2}$).