• 한국신뢰성학회지:신뢰성응용연구
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• 제12권2호
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• pp.67-78
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• 2012

An electric double-layer capacitor(EDLC) is an electrochemical capacitor with relatively high energy density, typically hundreds of times greater than conventional electrolytic capacitors. EDLCs are widely used for energy storage rather than as general-purpose circuit components. They have a variety of commercial applications, notably in energy smoothing and momentary-load devices, and energy-storage and kinetic energy recovery system devices used in vehicles, etc. This paper presents an accelerated degradation test of an EDLC with rated voltage 2.7V, capacitance 100F, and usage temperature $-40^{\circ}C{\sim}65^{\circ}C$. The EDLCs are tested at $50^{\circ}C$, $60^{\circ}C$, and $70^{\circ}C$, respectively for 1,750hours, and their capacitances are measured at predetermined times by constant current discharge method. The failure times are predicted from their capacitance deterioration patterns, where the failure is defined as 30% capacitance decrease from the initial one. It is assumed that the lifetime distribution of EDLC follows Weibull and Arrhenius life-stress relationship holds. The life-stress relationship, acceleration factor, and $B_{10}$ life at design condition are estimated by analyzing the accelerated life test data.

• 한국결정성장학회지
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• 제8권4호
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• pp.640-644
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• 1998

Sb/SiC(4H) 및 Ti/SiC(4H) 쇼트키 다이오드(SBD)를 제작하여 그 특성을 조사하였다. 용량-전압(C-V) 측정으로부터 얻은 n-형 SiC(4H)의 주개(donor) 농도는 약 $2.5{\times}10 ^{17}{\textrm}cm^{-3}$이었다. 순방향 전류-전압(I-V) 특성의 기울기로부터 얻은 Sb/SiC(4H) 쇼트키 다이오드의 이상계수는 1.31이었고, 역방향 항복전장(breakdown field)은 약 4.4$\times$102V/cm 이었다. 용량-전압(C-V) 측정으로부터 얻은 Sb/SiC(4H) SBD의 내부전위(built-in potential) 및 쇼트키 장벽 높이는 각각 1.70V 및 1.82V이었다. Sb/SiC(4H)의 장벽높이 1.82V는 Ti/SiC(4H)의 0.91V보다 높았다. 그러나 Sb/SiC(4H)의 전류밀도와 역방향 항복전장은 Ti/SiC(4H)의 것보다 낮았다. Ti/SiC(4H)는 물론 Sb/SiC(4H) 쇼트키 다이오드는 고전력 전자소자로서 유용하다.

• 한국전기전자재료학회논문지
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• 제17권1호
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• pp.21-26
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• 2004

Ultra-thin silicon dioxides were grown on p-type(100) oriented silicon employing rapid thermal dry oxidation technique at the temperature range of 850∼1050 $^{\circ}C$. The growth rate of the ultra-thin film was fitted well with tile model which was proposed recently by da Silva ＆ Stosic. The capacitance-voltage, current-voltage, characteristics were used to study the electrical properties of these thin oxides. The minimum interface state density around the midgap of the MOS capacitor having oxide thickness of 111.6 $\AA$ derived from the C-V curve was ranged from 6 to 10${\times}$10$^{10}$ /$\textrm{cm}^2$eV.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.222-227
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• 2004

The sub-bitline (SBL) sensing voltage of a cell and total cell array can be measured by the method of SBL voltage evaluation method. The MOSAID tester can collect all SBL signals. The hierarchical bitline of unit cell array block is composed of the cell array of 2k rows and 128 columns, which is divided into 32 cell array sections. The unit cell array section is composed of the cell array of 64 rows and 128 columns. The average sensing voltage with 2Pr value of $5{\mu}C/cm^2$ and SBL capacitance of 40fF is about 700mV at 3.0V operation voltage. That is high compensation method for capacitor size degradation effect. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than $5{\mu}C/cm^2$.

• 반도체디스플레이기술학회지
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• 제14권3호
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• pp.27-31
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• 2015

It was the electrical properties of ZnS treated by the annealing in a vaccum and an atmosphere conditions to reseached the leakage current effect of semiconductor devices. Most samples were shown the non-linear with unipolar properties, but the ZnS annealed at $100^{\circ}C$ in a vaccum was only observed no leakage current in a range of -20 V< voltage < 15 V. The crystallinity of ZnS with no leakage current was improved and optical property was also improved. Because the ambipolar characteristics and low leakage currents originated from the extension effect of a depletion width by electron-hole combination in the depletion layer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.1-7
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• 2014

A bidirectional transient voltage suppression (TVS) diode consisting of specially designed $p^--n^{{+}+}-p^-$ multi-junctions was developed using low temperature (LT) epitaxy and fabrication processes. Its electrostatic discharge (ESD) performance was investigated using I-V, C-V, and various ESD tests including the human body model (HBM), machine model (MM) and IEC 61000-4-2 (IEC) analysis. The symmetrical structure with very sharp and uniform bidirectional multi-junctions yields good symmetrical I-V behavior over a wide range of operating temperature of 300 K-450 K and low capacitance as 6.9 pF at 1 MHz. In addition, a very thin and heavily doped $n^{{+}+}$ layer enabled I-V curves steep rise after breakdown without snapback phenomenon, then resulted in small dynamic resistance as $0.2{\Omega}$, and leakage current completely suppressed down to pA. Manufactured bidirectional TVS diodes were capable of withstanding ${\pm}4.0$ kV of MM and ${\pm}14$ kV of IEC, and exceeding ${\pm}8$ kV of HBM, while maintaining reliable I-V characteristics. Such an excellent ESD performance of low capacitance and dynamic resistance is attributed to the abruptness and very unique profiles designed very precisely in $p^--n^{{+}+}-p^-$ multi-junctions.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2010년도 춘계학술대회 논문집
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• pp.1031-1032
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• 2010

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.85-86
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• 2007

A poly(vinylidene fluoride-trifluoroethyene) (P(VDF-TrFE)) copolymer thin film having ${\beta}$ phase was prepared by sol-gel method. The electrical properties of the film were studied to evaluate the possibility for appling to a ferroelectric random access memory. In order to characterize its electrical properties, we produced a MFS (metal-ferroelectric-semiconductor) structure by evaporation of Au electrodes. The C-V (capacitance-voltage) measurement revealed that the Au/P(VDF-TrFE)/Si structure with a 4 wt% film had a memory window width of about 0.5V for a bias voltage sweep of 1V.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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• pp.1924-1926
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• 2005

Poly(methyl methacrylate) (PMMA) is one of the promising representive of polymer gate dielectric for its high resistivity and sutible dielectric constant. PMMA (Mw=96700) films were prepared on p-Si by spin coating method. PMMA were coated compactively and flatly as observes by AFM. MIS(Al/PMMA/p-Si) structure was made and capacitance-voltage (C-V) and current-voltage (I-V) measurements were done with PMMA films for repeated annealing cycles at $100^{\circ}C$. 1-V measured at various delay times $(0{\sim}20sec)$ showed little change and the absence of hysteresis in the I-V characteristics with delay times, which eliminate the possibility of deep traps in the PMMA films. The observed thermal stability, smooth surfaces, dielectric constant, I-V behavior implies PMMA formed by spin coating can be used as an efficient gate dielectric layer in OTFTs.

• 한국전기전자재료학회논문지
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• 제30권10호
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• pp.615-624
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• 2017

This study investigated the various physical and electrical effects of silicon direct bonding. Direct bonding means the joining of two wafers together without an intermediate layer. If the surfaces are flat, and made clean and smooth using HF treatment to remove the native oxide layer, they can stick together when brought into contact and form a weak bond depending on the physical forces at room temperature. An IR camera and acoustic systems were used to analyze the voids and bonding conditions in an interface layer during bonding experiments. The I-V and C-V characteristics are also reported herein. The capacitance values for a range of frequencies were measured using a LCR meter. Direct wafer bonding of silicon is a simple method to fuse two wafers together; however, it is difficult to achieve perfect bonding of the two wafers. The direct bonding technology can be used for MEMS and other applications in three-dimensional integrated circuits and special devices.