• Transactions on Electrical and Electronic Materials
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• v.11 no.3
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• pp.120-125
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• 2010

For the fabrication of PMOS and integrated semiconductor devices, B, $BF_2$ and dual elements with B and $BF_2$ can be implanted in silicon. 15 keV B ions were implanted in silicon at $7^{\circ}$ wafer tilt and a dose of $3.0{\times}10^{16}\;cm^{-2}$. 67 keV $BF_2$ ions were implanted in silicon at $7^{\circ}$ wafer tilt and a dose of $3.0{\times}10^{15}\;cm^{-2}$. For dual implantations, 67 keV $BF_2$ and 15keV B were carried out with two implantations with dose of $1.5{\times}10^{15}\;cm^{-2}$ instead of $3.0{\times}10^{15}\;cm^{-2}$, respectively. For the electrical activation, the implanted samples were annealed with rapid thermal annealing at $1,050^{\circ}C$ for 30 seconds. The implanted profiles were characterized by using secondary ion mass spectrometry in order to measure profiles. The implanted and annealed results show that concentration profiles for the ${BF_2}^+$ implant are shallower than those for a single $B^+$ and dual ($B^+$ and ${BF_2}^+$) implants in silicon. This effect was caused by the presence of fluorine which traps interstitial silicon and ${BF_2}^+$ implants have lower diffusion effect than a single and dual implantation cases. For the fabricated diodes, current-voltage (I-V) and capacitance-voltage (C-V) were also measured with HP curve tracer and C-V plotter. Electrical measurements showed that the dual implant had the best result in comparison with the other two cases for the turn on voltage characteristics.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1284-1287
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• 2005

Peripheral pentacene region gives a significant influence on C-V characteristics of metal-oxide-pentacene capacitor structure. When the gate voltage goes toward negative, the effect of peripheral pentacene region becomes larger. Remaining gate DC bias constant and changing small signal frequency, the capacitance of peripheral pentacene changes along with frequency so that the total capacitance value also changes. The influence of peripheral pentacene region should be removed to measure accurate C-V characteristics, because it is hard to take into account the effect of the region quantitatively. After removing the influence of peripheral pentacene region, acceptor concentration, flat band voltage and depletion width of pentacene thin film are extracted from an accurate C-V curve as $1.58{\times}10^{17}cm^{-3}$, -1.54 V and 39.4 nm, respectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.7
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• pp.10-16
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• 1999

This paper describes a low voltage swing bus driver using FCSR(Feedback Control Swing voltage Reduction) which can control bus swing voltage within a few hundred of mV. It is proposed to reduce power consumption in On-chip interface, especially for MDL(Merged DRAM Logic) architecture wihich has wide and large capacitance bus. FCSR operates on differential signal dual-line bus and on precharged bus with block controlling fuction. We modeled driver and bus to scale driver size automatically when bus environment is variant. We also modeled coupling capacitance noise(crosstalk) of neighborhood lines which operate on odd mode with parallel current source to analysis crosstalk effect in the victim-line according as voltage transition in the aggressor-line and environment in the victim-line. We built a test chip which was designed to swing 600mV in bus, shows 70Mhz operation at 3.3V, using Hyundai 0.8um CMOS technology. FCSR operate with 250Mhz at 3.3V by Hspice simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.

• Journal of Sensor Science and Technology
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• v.23 no.3
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• pp.185-191
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• 2014

The width of depletion region in a varactor diode can be modulated by varying a reverse bias voltage. Thus, the preferred characteristics of depletion capacitance can obtained by the change in the width of depletion region so that it can select only the desirable frequencies. In this paper, the TV tuner varactor diode fabricated by hyper-abrupt profile control technique is presented. This diode can be operated within 3.3 V of driving voltage with capability of UHF band tuning. To form the hyperabrupt profile, firstly, p+ high concentration shallow junction with $0.2{\mu}m$ of junction depth and $1E+20ions/cm^3$ of surface concentration was formed using $BF_2$ implantation source. Simulation results optimized important factors such as epitaxial thickness and dose quality, diffusion time of n+ layer. To form steep hyper-abrupt profile, Formed n+ profile implanted the $PH_3$ source at Si(100) n-type epitaxial layer that has resistivity of $1.4{\Omega}cm$ and thickness of $2.4{\mu}m$ using p+ high concentration Shallow junction. Aluminum containing to 1% of Si was used as a electrode metal. Area of electrode was $30,200{\mu}m^2$. The C-V and Q-V electric characteristics were investigated by using impedance Analyzer (HP4291B). By controlling of concentration profile by n+ dosage at p+ high concentration shallow junction, the device with maximum $L_F$ at -1.5 V and 21.5~3.47 pF at 0.3~3.3 V was fabricated. We got the appropriate device in driving voltage 3.3 V having hyper-abrupt junction that profile order (m factor) is about -3/2. The deviation of capacitance by hyper-abrupt junction with C0.3 V of initial capacitance is due to the deviation of thermal process, ion implantation and diffusion. The deviation of initial capacitance at 0.3 V can be reduced by control of thermal process tolerance using RTP on wafer.

• Journal of the Korean Vacuum Society
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• v.10 no.4
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• pp.440-448
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• 2001

The operation properties of DBD plasma reactors were observed by using 20 kV square pulse at the cylindrical and planar type of reactors in the condition of air pressure. The optimum operation frequency $f_0$ which optimizes the efficiency of operation was found as such $f_0\proptoexp(-C)$ when the current-voltage curve and charge-voltage curve were observed. Using these properties the dissipated power was evaluated. The dissipated power at the optimum frequency of operation was varied as the value of capacitance which is dependent on the structure and the dielectric material of the reactor, and had the maximum value at the specific value of capacitance. With these value of capacitance, DBD reactors which has a high level of efficiency can be formed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.311-316
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• 2010

$Zr_{0.7}Sn_{0.3}TiO_4$ (ZST) thin films were fabricated by metal-organic decomposition, and their dielectric properties were investigated in order to evaluate their potential use in passive capacitors for rf and analog/mixed signal integrated circuits. The ZST thin film annealed at the temperature of $800^{\circ}C$ showed a dielectric constant of 27.3 and a dielectric loss of 0.011. The capacitor using the ZST film had quadratic and linear voltage coefficient of capacitance (VCC) of -65 ppm/$V^2$ and -35 ppm/V at 100 kHz, respectively. It also exhibited a good temperature coefficient of capacitance (TCC) value of -32 ppm/$^{\circ}C$ at 100 kHz.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.711-714
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• 2008

Metal-oxide-semiconductor (MOS) capacitors were fabricated to investigate the plasma damage caused by reactive ion etching (RIE) on (100) oriented silicon-on-insulator (SOI) substrates. The thickness of the top-gate oxide, SOI, and buried oxide layers were 10 nm, 50 nm, and 100 nm, respectively. The MOS/SOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching. The measured C-V curves were compared to the numerical results from corresponding 2-dimensional (2-D) structures by using a Silvaco Atlas simulator.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.785-787
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• 1988

The capacitance-voltage (C-V) chracteristics of thin nitrided thermal oxides prepared by rapid termal nitridation(RTN) have been studied. The threshold voltages were calculated using C-V measurement and found to vary as the concentration of acceptor and the thickness of oxynitride. When the Si02 films were annealed in NH3 a decrease in the positive oxide charge due to Si-N bond was observed. In the case applied frequency is high and low, the high frequency depletion capacitance was higher than that of low frequency, which is indicative of high frequency surface conduction by mobile surface charge.

• Journal of Electrical Engineering and Technology
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• v.9 no.1
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• pp.280-285
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• 2014

In order to evaluate the insulation deterioration in the stator windings of five gas turbine generators(137 MVA, 13.8 kV) which has been operated for more than 13 years, diagnostic test and AC dielectric breakdown test were performed at phases A, B and C. These tests included measurements of AC current, dissipation factor, partial discharge (PD) magnitude and capacitance. ${\Delta}I$ and ${\Delta}tan{\delta}$ in all three phases (A, B and C) of No. 1 generator stator windings showed that they were in good condition but PD magnitude indicated marginally serviceable and bad level to the insulation condition. Overall analysis of the results suggested that the generator stator windings were indicated serious insulation deterioration and patterns of the PD in all three phases were analyzed to be internal, slot and spark discharges. After the diagnostic test, an AC overvoltage test was performed by gradually increasing the voltage applied to the generator stator windings until electrical insulation failure occurred, in order to determine the breakdown voltage. The breakdown voltage at phases A, B and C of No. 1 generator stator windings failed at 28.0 kV, 17.9 kV, and 21.3 kV, respectively. The breakdown voltage was lower than that expected for good-quality windings (28.6 kV) in a 13.8kV class generator. In the AC dielectric breakdown and diagnostic tests, there was a strong correlation between the breakdown voltage and the voltage at which charging current increases abruptly ($P_{i1}$, $P_{i2}$).