• Korean Journal of Metals and Materials
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• v.50 no.8
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• pp.613-618
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• 2012

We report on electrical and mechanical properties of silicon nitride ($SiN_x$) films deposited by a plasma enhanced chemical vapor deposition (PECVD) method at $200^{\circ}C$ from $SiH_4$ highly diluted in $N_2$. The films were also prepared from $SiH_4$ diluted in He for comparison. The $N_2$ dilution was also effective in improving adhesion of the $SiN_x$ films, fascilitating construction of thin film transistors (TFTs). Metal-insulator-semiconductor (MIS) and Metal-insulator-Metal (MIM) structures were used for capacitance-voltage (C-V) and current-voltage (I-V) measurements, respectively. The resistivity and breakdown field strength of the $SiN_x$ films from $N_2$-diluted $SiH_4$ were estimated to be $1{\times}10^{13}{\Omega}{\cdot}cm$, 7.4 MV/cm, respectively. The MIS device showed a hysteresis window and a flat band voltage shift of 3 V and 0.5 V, respectively. The TFTs fabricated by using these films showed a field-effect mobility of $0.16cm^2/Vs$, a threshold voltage of 3 V, a subthreshold slope of 1.2 V/dec, and an on/off ratio of > $10^6$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.2
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• pp.126-129
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• 2006

We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.

• Carbon letters
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• v.16 no.2
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• pp.78-85
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• 2015

Activated carbons (ACs) were prepared by activation of coal tar pitch (CTP) in the range of $700^{\circ}C-1000^{\circ}C$ for 1-4 h using potassium hydroxide (KOH) powder as the activation agent. The optimal activation conditions were determined to be a CTP/KOH ratio of 1:4, activation temperature of $900^{\circ}C$, and activation time of 3 h. The obtained ACs showed increased pore size distribution in the range of 1 to 2 nm and the highest specific capacitance of 122 F/g in a two-electrode system with an organic electrolyte, as measured by a charge-discharge method in the voltage range of 0-2.7 V. In order to improve the performance of the electric double-layer capacitor electrode, various mixtures of CTP and petroleum pitch (PP) were activated at the optimal activation conditions previously determined for CTP. Although the specific capacitance of AC electrodes prepared from CTP only and the mixtures of CTP and PP was not significantly different at a current density of 1 A/g, the AC electrodes from CTP and PP mixtures showed outstanding specific capacitance at higher current rates. In particular, CTP-PP61 (6:1 mixture) had the highest specific capacitance of 132 F/g, and the specific capacitance remained above 90% at a high current density of 3 A/g. It was found that the high specific capacitance could be attributed to the increased micro-pore volume of ACs with pore sizes from 1 to 2 nm, and the high power density could be attributed to the increased meso-pore volume.

• Journal of Electrical Engineering and Technology
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• v.10 no.6
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• pp.2364-2367
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• 2015

In this study, we fabricated an electrolyte-insulator-metal (EIM) device incorporating a high-k Al₂O₃ sensing membrane using a porous anodic aluminum oxide (AAO) through a two-step anodizing process for pH detection. The structural properties were observed by field-emission scanning electron microscopy (FE-SEM) and X-ray diffraction patterns (XRD). Electrochemical measurements taken consisted of capacitance-voltage (C-V), hysteresis voltage and drift rates. The average pore diameter and depth of the AAO membrane with a pore-widening time of 20 min were 123nm and 273.5nm, respectively. At a pore-widening time of 20 min, the EIM device using anodic aluminum oxide exhibited a high sensitivity (56mV/pH), hysteresis voltage (6.2mV) and drift rate (0.25mV/pH).

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.221-225
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• 2003

The MFIS-FET(Field Effect Transistor) devices using $BLT/Y_2O_3$ buffer layer on p-Si(100) substrates were fabricated by the Sol-Gel method and conventional memory processes. The crystal structure, morphologies and electrical properties of prepared devices were investigated by using various measuring techniques. From the C-V(capacitance-voltage) data at 5V, the memory window voltage of the $Pt/BLT/Y_2O_3/si$ structure decreased from 1.4V to 0.6V with increasing the annealing temperature from $700^{\circ}C\;to\;750^{\circ}C$. The drain current (Ic) as a function of gate voltages $(V_G)$ for the $MFIS(Pt/BLT/Y_2O_3/Si(100))-FET$ devices at gate voltages $(V_G)$ of 3V, 4V and 5V, the memory window voltages increased from 0.3V to 0.8V as $V_G$ increased from 3V to 5V.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.206.1-206.1
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• 2015

최근에 금속산화물을 증착하는 방법으로 용액공정이 주목 받고 있다. 용액 공정은 대기압에서 매우 간단한 방법으로 복잡한 공정과정을 요구하지 않기 때문에 박막을 경제적으로 간단하게 형성할 수 있다. 하지만 용액공정을 통해 형성한 박막에는 소자의 특성을 열화 시키는 solvent와 탄소계열의 불순물을 많이 포함하고 있어 고온의 열처리가 필수적이다. 박막의 품질을 향상시키기 위해서 다양한 열처리 방법들이 이용되고 있으며, 일반적인 열처리 방법으로는 furnace를 이용한 conventional thermal annealing (CTA)이 많이 이용되고 있다. 하지만, 최근에는 microwave를 이용한 공정이 주목 받고 있다. Microwave energy는 CTA보다 효과적으로 비교적 낮은 온도에서 높은 열처리 효과를 나타낸다. 본 실험은 n-type Silicon 기판에 solution-ZrO2 산화막을 형성 후, oven baking을 한 뒤, CTA와 microwave를 이용하여 solvent와 불순물을 제거 하였다. 전기적 특성을 확인하기 위해 solution ZrO2 산화막 위에 E-beam evaporator를 이용해 Ti 금속 전극을 증착하여 Metal-Oxide-Semiconductor (MOS) capacitor를 제작하였다. 다음으로, PRECISION SEMICONDUCTOR PARAMETER ANALYZER (4156B)를 이용하여, capacitance-voltage (C-V) 특성 및 current-voltage (I-V) 특성을 비교하였다. 다음으로, CTA를 통하여 제작한 소자와 전기적 특성을 비교하였다. 그 결과, Microwave irradiation으로 열처리한 MOS capacitor 소자에서 capacitance 값과 flat band voltage, hysteresis 등이 개선되는 효과를 확인하였다. Microwave irradiation 열처리는 100oC 미만의 온도에서 공정이 이루어짐에도 불구하고 시료 내에서의 microwave 에너지의 흡수가 CTA 공정에서의 열에너지 흡수보다 훨씬 효율적으로 이루어지며, 결과적으로 ZrO2 용액의 불순물과 solvent를 낮은 온도에서 제거하여 고품질 박막 형성에 매우 효과적이라는 것을 나타낸다. 따라서, microwave irradiation 열처리 방법은 비정질 산화막이 포함되는 박막 transistor 소자 제작에 대하여 결정적인 열처리 방법이 될 것으로 기대한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.49-49
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• 2008

ZnO-based varistors have been widely used for voltage stabilization or transient surge suppression in electric power systems and electronic circuits. Recently, It has reported that the varistor behavior with nonlinear coefficient of 6~17 in Mn-doped ZnO. In this study we have chosen the composition of ZnO-$TeO_2-Mn_3O_4$ (ZTM) system to the purpose of whether varistor behavior appeared in doped ZnO by the solid state sintering or not. We investigated the sintering and electric properties of 0.5~3.0 at% Mn doped ZnO-1.0 at% $TeO_2$ system. Electrical properties, such as current-voltage (I-V), capacitance-voltage (C-V), and impedance spectroscopy were conducted. $TeO_2$ itself melts at $732^{\circ}C$ in air but forms the $ZnTeO_3$ phase with ZnO as increasing temperature and therefore retards the densification of ZnO to $1000^{\circ}C$. The average grain size of sintered samples was at about $3{\mu}m$ and decreased with increasing Mn contents. It was found that a good varistor characteristics were developed in ZTM system sintered at $1100^{\circ}C$ (nonlinear coefficient $\alpha$ ~ 60). The results of C-V characteristics such as barrier height ($\Theta$), donor density ($N_d$), depletion layer (W), and interface state density ($N_t$) in ZTM ceramics were $4\times10^{17}cm^{-3}$, 0.7 V, 40 nm, and $1.6\times10^{12}cm^{-2}$, respectively. It will be discussed about the stability and homogeneity of grain boundaries using distribution parameter ($\alpha$) simulated with the Z(T)"-logf plots in ZTM system.

• Korean Journal of Materials Research
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• v.11 no.4
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• pp.290-293
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• 2001

The SrBi$_2$Nb$_2$O$_{9}$ (SBN) thin films were deposited on p-type(100) Si substrates by rf magnetron sputtering to confirm the Possibility of Pt/SBN/Si structure for the application of nondestructive read out ferroelectric random access memory (NDRO- FRAM). The SBN thin films were deposited by co-sputtering method with Sr$_2$Nb$_2$O$_{7}$ (SNO) and Bi$_2$O$_3$ ceramic targets. The SBN thin films deposited at room temperature were annealed at $700^{\circ}C$ for 1hr in $O_2$ ambient. The structural and electrical properties of SBN with different power ratios of targets were measured by x-ray diffraction(XRD), scanning electron microscopy(SEM), capacitance-voltage(C-V), and current-voltage(I-V). The C-V curves of the SBN films showed hysteresis curves of a clockwise rotation showing ferroelectricity. When the Power ratio of the SNO/Bi$_2$O$_3$ targets was 120 W/100 W, the SBN thin films had excellent electrical properties. The memory window of SBN thin film was 1.8 V-6.3 V at applied voltage of 3 V-9 V and the leakage current density was 1.5 $\times$ 10$^{-7}$ A/$\textrm{cm}^2$ at applied voltage of 5 V The composition of SBN thin films was analysed by electron probe X-ray micro analyzer(EPMA) and the atomic ratio of Sr:Bi:Nb with pawer ratio of 120 W/100 W was 1:3:2.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.2
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• pp.7-12
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• 2003

The $Bi_{3.3}La_{0.7}O_{12}$(BLT) capacitors with Metal-Ferroelectric-Insulator-Silicon structure were prepared on $SiO_2/Si$ substrates by using sol-gel method. The BLT thin films annealed at $650^{\circ}C$ and $700^{\circ}C$ showed randomly oriented perovskite crystalline structures. The full with at half maximum (FWHM) of the (117) main peak was decreased from $0.65^{\circ}$ to $0.53^{\circ}$ with increasing the annealing temperature from $650^{\circ}C$ to $700^{\circ}C$, indicating the improvement in the crystalline quality of the film. In addition, the grain size and $R_rms$ , values were increased with increasing the annealing temperatures, showing the rough film surface at higher annealing temperatures. From the capacitance-voltage (C-V) measurements, the memory window voltage of the BLT film annealed at $700^{\circ}C$ was found to be about 0.7 V at an applied voltage of 5 V. The leakage current density of the BLT film annealed at $700^{\circ}C$ was about $3.1{\times}10^{-8}A/cm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.159-167
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• 2005

Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the $Schr{\ddot{o}}dinger$ and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.