• Journal of KIISE:Computer Systems and Theory
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• v.29 no.12
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• pp.680-686
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• 2002

In deep-submicron (BSM) design, coupling effects between wires on the bus cause serious problems such as crosstalk delay, noise, and power consumption. Most of the previous works on bus encoding are targeted either to minimize tile power consumption on bus or to minimize the crosstalk delay, but not both. In this paper, we propose a new bus encoding algorithm that minimizes the power consumption on bus and eliminates the crosstalk delay simultaneously. We formulate and solve the problem by minimizing a weighted sum of the self transition and cross-coupled transition activities on bus From experiments using a set of benchmark designs. it is shown that the proposed encoding technique consumes at least 15% less power over the existing techniques, while completely eliminating the crosstalk delay.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.12B
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• pp.1548-1555
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• 2011

In ultra-deep submicron technology, minimization of propagation delay and power consumption on buses is one of the most important design objectives in system-on-chip (SOC) design. Crosstalk between adjacent wires on the bus may create a significant portion of propagation delay. Elimination or minimization of such faults is crucial to the performance and reliability of SOC designs. Most of the previous works on bus encoding are targeted either to minimize the bus switching or minimize the crosstalk delay, but not both. This paper proposes a new bus encoding scheme which can adaptively select one of functions "invert" and "logic-convert" according the number of bus switching on an encoded 4-bit cluster. This scheme leads to minimization of both crosstalk and bus switching. In experiment result, our proposed encoding technique consumes about 25% less power over the previous, while completely eliminating the crosstalk delay.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.23-30
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• 1998

We present a partial bus-invert coding scheme for system-level power optimization. In the proposed scheme, we select a sub-group of bus lines involved in bus encoding to avoid unnecessary inversion of bus lines not in the sub-group thereby reducing the total number of bus transitions. We propose a heuristic algorithm that selects the sub-group of bus lines for bus encoding. Experiments on benchmark examples indicate that the partial bus-invert coding reduces the total bus transitions by 62.6% on the average, compared to that of the unencoded patterns. We also compare the performance of the proposed heuristic algorithm with that of simulated annealing, which shows that it is highly efficient.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.36-44
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• 2007

This paper presented a hybrid ternary encoding scheme using 3-valued logic. It can adapt to the delay-insensitive(DI) model. We designed an asynchronous wrapper for the hybrid ternary encoding scheme to communicate with various asynchronous encoding schemes. It reduced about 50% of transmission lines and power consumption compared with the conventional 1-of-4 and ternary encoding scheme. The proposed wrappers were designed and simulated using the $0.18-{\mu}m$ standard CMOS technology. As a result, the asynchronous wrapper operated over 2 GHz communicating with a system bus. Moreover, the power dissipation of the system bus adapted the hybrid ternary encoding logic decreases 65%, 43%, and 36% of the dual-rail, 1-of-4, and ternary encoding scheme, respectively. The proposed data encoding scheme and the wrapper circuit can be useful for asynchronous high-speed and low-power asynchronous interface.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10b
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• pp.264-268
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• 2007

연결선(interconnect) 사이의 간섭으로 발생하는 crosstalk 지연시간(delay)을 제거하기 위한 두 가지의 방법을 제안 한다. (1) 체계적인 코드를 생성해내는 방법으로 crosstalk 지연시간(delay) 유발 경우를 두 가지의 종류로 분류하여 각각에 대해 버스(bus) 비트 수의 증가에 따른 analytic 한 코드 생성 공식을 유도하였다; (2) 부-버스(sub-bus) 간에 발생하는 crosstalk 지연시간(delay)을 기존의 방법에 비해 보다 효율적으로 제거하는, 즉 추가적인 차단 라인 (또는 complement 비트 라인)를 감소시키는 방법을 제안 한다. 두 연구 결과는 연결선 상의 데이터 전송에 따른 신뢰성, 지연시간 및 전력 소모 증가를 유발하는 crosstalk를 차단하는 엔코딩 기법으로 유용하게 사용될 것으로 보인다.

• Proceedings of the KSR Conference
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• 2007.05a
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• pp.1735-1740
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• 2007

Communication network in KTX (Korea Train eXpress), the express train system, has to transmit status variables periodically within tens of seconds and real-time control informations which has short reply like status transition or alarm. KTX uses $Tornad^*$ (TOken Ring Network Alsthom Device) network for this purpose. This network can send and receive messages which enable express train applications embedded in intelligence boards to communicate by itself. Layer 1, 2 of $Tornad^*$ is implemented with differential manchester encoding and IEEE 802.4 standard(token bus standard) respectively. To implement layer 1 and 2, we implemented twisted pair modem using FPGA for layer 1 and used MC68824 from Motorola for layer 2. MC68824 bus arbitration and memory controller is implemented using CPLD.

• 전자공학회논문지 IE
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• v.45 no.3
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• pp.5-12
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• 2008

We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10a
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• pp.623-628
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• 1990

This paper describes the design of EFbus(ETRI Fieldbus), EFbus was designed from the interim results of international Fieldbus standardization in IEC (International Electrotechnical Commission) and proposals of many companies. The design was performed and described on the basis of three layered architecture. Application layer S/W runs on IBM PC and provides services which is similar ED MMS in MAP to user application Data linklayer runs on Intel's iDCX96 real time executive and uses centralized media accesscontrol method. Physical layer uses Manchester encoding & decoding, twisted pair fines and RS485 electrical standard.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.2015-2020
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• 2008

Real-time communication network is important for KTX high speed train system because small problem can make a huge accident. Communication network for KTX high speed train system consists of IEEE 802.4 token bus network and FM0 encoding. The network device is developed by using MC68824 TBC, MC68185 TPM and MC68020 MPU. The network device make available to analysis of the network protocol among vehicles for Kyung-Boo high-speed train system.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.718-720
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• 2005

딥-서버마이크론 기술에서, 버스 상에서의 전력 소모를 최소화하는 것은 가장 중요한 설계 목표들 가운데 하나이다. 전력 소모를 줄이기 위해 일반적으로 사용되고 있는 효과적인 기법들은 근본적으로 데이터 압축 또는 데이터 인코딩을 이용하고 있지만 압축과 인코딩을 모두 사용한 기법은 현재까지 알려져 있지 않다. 본 논문은 버스에서의 데이터 전송 시 발생하는 전력소모량을 크로스톡 지연을 완전히 제거함과 동시에 최대한 줄이는 통합된 데이터 압축 및 인코딩 알고리즘을 제안한다. 전력 소모를 줄이는 문제를 셀프 천이와 크로스-커플된 천이 양에 대한 가중 합을 최소화하는 문제로 형상화하여 풀었으며, 이 과정에서 자주-인용 데이터에 기반한 압축과 셀프-쉴드 인코딩이라는 개념을 활용하였다. 벤치마크를 사용한 실험에서 우리는 제안한 방법을 사용하면, 기존의 순차적인 압축 및 인코딩 적용 방식보다 $7.9\%-39.4\%$ 더 적은 전력 소모를 가짐을 알 수 있었다.